Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 4/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

2.2. Video Packets

For the full variant Intel FPGA streaming video protocol, TUSER[1] is low in cycle 0 to indicate this packet is a video packet. For the lite protocol, TUSER[1] indicates the field polarity, and must be constant throughout the packet. A low indicates this packet is either from a progressive frame or an interlaced field of type F0. A high indicates this packet is from an interlaced field of type F1.

TUSER[0] is decoded in the first valid cycle of the packet. The start of a new video field is indicated when TUSER[0] is high in this cycle.

Video packets carry pixel data. Both full and lite variants of the protocol use video packets. Video packets may be 1 or more beats in length.

Figure 16. A video packet for the first line of a new video field (1x30bit pixel interface) The figure shows an example video packet for the first line of a video field. TUSER[0] is indicating this line is the start of a new video field.

In the example, TUSER is 4 bits wide, as the 30 bits of pixel data occupy 4 bytes of TDATA. In the first beat of the transfer, TUSER indicates a new field of video by asserting TUSER[0] high and TUSER[1] low to indicate a video packet. Other TUSER bits, e.g. TUSER[3:2], can take any value, but IPs compliant with the Intel FPGA streaming protocol do not have to propagate these values and it is recommended that these are held low. TLAST indicates the last pixel in each line.

TUSER[0] indicates the start of a new video field, but you cannot tell which video packet is the last line of the field. The full variant of the protocol allows the detection of the end of the current video field by the arrival of an end of field packet. The lite variant has no signaling for the end of the current field, but TUSER[0] indicates the first pixel of the next field.

Figure 17. Video frame transmission (lite variant)The figure shows an example of progressive video frame propagation for lite variants.

Lite variants have no metapackets so TUSER[1] is always low for progressive video. The video packet for the first line of each frame is indicated by TUSER[0].

Full variants add image information and end of field packets to describe the frame properties and mark the end of each frame.

Figure 18. Video frame transmission (full variants)

Section Content
TDATA Pixel Packing
RGB Pixel Packing
YCbCr 444 Pixel Packing
YCbCr 422 Pixel Packing
YCbCr 420 Pixel Packing
Four-Channel Video Pixel Packing
Packing with Multiple Pixels in Parallel
Multiple Pixels in Parallel and Empty Pixels
YCbCr 422 Video with Multiple Pixels in Parallel
Packing RGB444 onto an RGB888 Interface
Packing with Less than 8 bits per Symbol Natively
Interlaced Fields

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