Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Document Table of Contents

1.2. Data Exchange

The TVALID and TREADY handshake determines when information passes across the AXI4-Stream. A two-way flow control mechanism enables both the input and output interfaces to control the rate at which the data and control information transmits across the interface.

For a valid transfer to occur the output interface and input interface must assert TVALID and TREADY respectively for one clock cycle. The output interface must not wait until the input interface asserts TREADY before asserting TVALID. When the output interface asserts TVALID, it keeps asserted until the handshake occurs. Other signals (TDATA, TUSER, TLAST) must remain stable. An input interface can wait for TVALID to be asserted before asserting the corresponding TREADY. If an input interface asserts TREADY, it can deassert TREADY before TVALID is asserted.

A successful handshake occurs when:

  • TVALID is asserted before TREADY
  • TREADY is asserted before TVALID
  • TREADY and TVALID asserted on the same cycle

The figures do not show TUSER or TLAST but these signals also follow the same rules for validity as shown for TDATA.

Figure 1. AXI4-Stream Handshake: TVALID before TREADY The figure shows the output interface producing data and asserting the TVALID signal active-high.

When the output interface asserts TVALID, the data from the output interface must remain unchanged until the input interface drives the TREADY signal active-high, indicating that it can accept the data. In this case, transfer takes place when the input interface asserts TREADY active-high.

Figure 2. AXI4-Stream Handshake: TREADY before TVALID The figure shows the input interface driving TREADY active-high before the data and control information is valid.

The destination can accept the data and control information in a single clock cycle. In this case, transfer takes place when the output interface asserts TVALID active-high.

Figure 3. AXI4-Stream Handshake: TVALID and TREADY asserted at the same time The figure shows both output and input interfaces asserting TVALID and TREADY active-high in the same clock cycle, respectively. In this case, data transfer takes place in the same cycle.