Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

1.2. Data Exchange

The TVALID and TREADY handshake determines when information passes across the AXI4-Stream. A two-way flow control mechanism enables both the input and output interfaces to control the rate at which the data and control information transmits across the interface.

For a valid transfer to occur the output interface and input interface must assert TVALID and TREADY respectively for one clock cycle. The output interface must not wait until the input interface asserts TREADY before asserting TVALID. When the output interface asserts TVALID, it keeps asserted until the handshake occurs. Other signals (TDATA, TUSER, TLAST) must remain stable. An input interface can wait for TVALID to be asserted before asserting the corresponding TREADY. If an input interface asserts TREADY, it can deassert TREADY before TVALID is asserted.

A successful handshake occurs when:

  • TVALID is asserted before TREADY
  • TREADY is asserted before TVALID
  • TREADY and TVALID asserted on the same cycle

The figures do not show TUSER or TLAST but these signals also follow the same rules for validity as shown for TDATA.

Figure 1. AXI4-Stream Handshake: TVALID before TREADY The figure shows the output interface producing data and asserting the TVALID signal active-high.

When the output interface asserts TVALID, the data from the output interface must remain unchanged until the input interface drives the TREADY signal active-high, indicating that it can accept the data. In this case, transfer takes place when the input interface asserts TREADY active-high.

Figure 2. AXI4-Stream Handshake: TREADY before TVALID The figure shows the input interface driving TREADY active-high before the data and control information is valid.

The destination can accept the data and control information in a single clock cycle. In this case, transfer takes place when the output interface asserts TVALID active-high.

Figure 3. AXI4-Stream Handshake: TVALID and TREADY asserted at the same time The figure shows both output and input interfaces asserting TVALID and TREADY active-high in the same clock cycle, respectively. In this case, data transfer takes place in the same cycle.
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