Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Document Table of Contents

2.2.1. TDATA Pixel Packing

Intel FPGA streaming video packets should follow these rules:
  • Ensure pixels comprise between 1 and 4 symbols of pixel data.
  • Pack video packet data across the TDATA bytes with the LSB of the first symbol of the first pixel in bit 0.
  • Byte align each pixel when packing multiple pixels in parallel.
  • When a pixel does not perfectly fill a given number of bytes, pad MSBs with undefined data.
  • For less than 16 bits of pixel data (for example single pixel 10 bit mono video), pad bits from the MSB of pixel data to bit 15 with undefined data
Figure 19. Example – 10 bit mono data packed to Intel FPGA streaming protocol minimum TDATA width

Parameterize video pipelines using the protocol for a specific number of bits per symbol, pixels in parallel, and color space. These parameters specify the size of the TDATA and TUSER buses.

The protocol also allows for video data of different color spaces to propagate down compatible pipelines by virtue of the CSP and SubSa fields in image information packets.