Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Document Table of Contents

4.4.5. Synchronous Pixel Clock Rates I/O Interfaces

This type of video interface has both transmitter and receiver video I/Os running based on the same video clock. The full-raster protocol allows you to configure compatible video interfaces with no TREADY signal so that they cannot accept backpressure.

Consequently, the receiver full-raster interface should accept data transfers on the bus in definite time intervals, defined by the sampling video rate, which allows either:

  • Removing TREADY from the video interface. It does not need it because of the lack of backpressure support
  • Driving TREADY signal high all the time.

Having a streaming full-raster compatible interface that does not support backpressure, allows you to move data between IPs using the native video receiver clock frequency. For example, 148.5 MHz for 1920x1080p60 with 1 pixel in parallel or 297 MHz for 3840x2160p60 with 2 pixels in parallel.

Figure 54.  Streaming Full Raster Data Rate Matching: Full-Rate Case

The figure shows a live video stream passing straight from a clocked-video domain to a streaming full-raster domain. All modules run at the same frequency (CLK receiver) and can accept the expected input data rate. None of the modules in the pipeline support backpressure. TREADY is active-high all the time, so Module A, Module B and Module C can accept data transfers on the TDATA bus at the specified data rate dictated by CLK receiver signal.