Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

2.1. Metapackets (Full Variants)

Metapackets usually carry control information. Use metapackets in the full variant of the Intel FPGA streaming video protocol but not in the lite variant. Metapacket lengths are between 1 to 4 beats (clock cycles).
Figure 6. Intel FPGA streaming metapacket (full variant only)The figure shows a packet where TUSER[1] is high in beat 0, which shows this packet is a metapacket.

TUSER[1] is decoded during the first valid beat of the packet (beat 0 in the figure) and a high value indicates the start of a new metapacket. TUSER[0] and TUSER[1] should be low for the remainder of the packet.

Table 2.  TUSER bits decode (Full variants only)
TUSER[1:0] Meaning
00 Video packet (from either an interlaced (F0 or F1) field or progressive frame).
01 Video packet (start of either an interlaced (F0 or F1) field or progressive frame).
10 Metapacket.
11 Reserved.

Metapackets carry their information in the low 16 bits of TDATA. The protocol does not require any additional TDATA bits. The protocol defines different metapacket types, each with a 5 bit packet identifier carried in the 5 LSBs of the first beat of the packet.

Figure 7. Metapacket format

The protocol classifies metapackets into image information, end of field, auxiliary control and user-defined auxiliary control packets.

Table 3.  Metapacket types
Packet identifier Packet type
0 Image information
1 End of field
Auxiliary control packets
2 Timestamp
3 Register update
4 Commit
5-15 Reserved
User-defined auxiliary control packets
16 - 31 General-purpose user

Section Content
Image Information Packets
End-of-Field Packets
Auxiliary Control Packets

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