Intel® FPGA Streaming Video Protocol Specification

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ID 683397
Date 4/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Packing RGB444 onto an RGB888 Interface 2.2.11. Packing with Less than 8 bits per Symbol Natively 2.2.12. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

2.2.11. Packing with Less than 8 bits per Symbol Natively

You should always size the Intel video streaming interface for the largest BPS that you want to support.

If RGB444 is the largest video data that you transmit over the Intel video streaming interface, you need not space the data bits as in the previous figure. You can size the tdata bus to accommodate the 12 bits of video data plus another 4 bits of padding to satisfy the minimum tdata bus width requirement of 16 bits. The video data packs naturally.

Figure 34. Video data packing naturally

The standard rules for pixel packing still apply. A 2 pixels-in -parallel interface of RGB444 requires you to pad bits 15 to 12 to meet the requirement that each pixel begins on a byte boundary. Therefore, the total tdata size for a 2 PiP RGB444 interface is 28 bits: 16 bits for the first 12 bits of pixel data plus the 4 padding bits plus another 12 bits for the second pixel. You do not need to pad this second pixel as it is over the 16 bits minimum tdata width requirement and you are not packing a third pixel above the second one.

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