Intel FPGA Streaming Video Protocol Specification

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ID 683397
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the Intel FPGA Streaming Video Protocol 2. Intel FPGA Streaming Video Protocol Description 3. Intel FPGA Streaming Video Protocol Rules 4. Intel FPGA Streaming Video Full-Raster Protocol 5. Document Revision History for Intel FPGA Streaming Video Protocol Specification
1. About the Intel FPGA Streaming Video Protocol x
1.1. Protocol Signals 1.2. Data Exchange
2. Intel FPGA Streaming Video Protocol Description x
2.1. Metapackets (Full Variants) 2.2. Video Packets
2.1. Metapackets (Full Variants) x
2.1.1. Image Information Packets 2.1.2. End-of-Field Packets 2.1.3. Auxiliary Control Packets
2.1.3. Auxiliary Control Packets x
2.1.3.1. Timestamp Packets 2.1.3.2. Register Update Packets 2.1.3.3. Commit Packets 2.1.3.4. User-defined Auxiliary Control Packets
2.2. Video Packets x
2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Interlaced Fields
3. Intel FPGA Streaming Video Protocol Rules x
3.1. Rules for Packets 3.2. Rules for IPs
3.1. Rules for Packets x
3.1.1. Auxiliary Control Packet Rules
4. Intel FPGA Streaming Video Full-Raster Protocol x
4.1. Full-Raster Frame Structure 4.2. Full-Raster Start of Frame 4.3. Full-Raster TDATA Signal Layout 4.4. Full-Raster TREADY Signal 4.5. Full-Raster I/O Signals
4.4. Full-Raster TREADY Signal x
4.4.1. Full-Raster TREADY Handshake Process 4.4.2. Optional TREADY Signal: Receiver Interface 4.4.3. Optional TREADY Signal: Transmitter Interface 4.4.4. Optional Backpressure 4.4.5. Synchronous Pixel Clock Rates I/O Interfaces 4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces
1. About the Intel FPGA Streaming Video Protocol
2. Intel FPGA Streaming Video Protocol Description
3. Intel FPGA Streaming Video Protocol Rules
4. Intel FPGA Streaming Video Full-Raster Protocol
5. Document Revision History for Intel FPGA Streaming Video Protocol Specification

2.2.6. Four-Channel Video Pixel Packing

The Intel FPGA streaming video protocol specifies a packing scheme for four-channel video. Typically, four-channel video uses the fourth channel for an alpha or transparency layer.
Figure 24. 8 bit RGBA video packet
Figure 25. 8 bit 422 YCbCrA video packet
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