Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Document Table of Contents

2.2.10. Packing RGB444 onto an RGB888 Interface

The protocol imposes no bounds on the BPS values it supports. However, any physical implementation of the protocol necessarily imposes restrictions on those BPS values.

You can only size a physical AXI to suit a particular BPS. However the protocol allows for transport of video with lower BPS values by specifying the lower BPS in the image information packet and packing the video into the MSBs of the tdata bus.

Figure 33. A physical AXI with a 24 bit native tdata busThe figure shows a physical AXI implementation for video with BPS=8. A second frame of RGB444 (BPS=4) video follows a frame of RGB24 video. Each frame's preceding image information packet specifies the BPS for that frame. tdata holds the MSBs for each symbol in the MSB positions for the native 8-bit video symbols. In this figure, they are bits 7, 15 and 23.