Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Document Table of Contents

4.4.6. Asynchronous Pixel Clock Rates I/O Interfaces

This type of video interface assumes that the transmitter generates video data with a slower or faster pixel clock rate compared to the receiver video interface.

Moving video data between two different clock domains is always challenging. You must apply clock domain crossings (CDC). The TVALID and TREADY flow-controlled AXI4-S video interface can cause control-flow problems on the video datapath, in either of the following two scenarios:

  • Clock-skew matching where video receiver or transmitter and video processing clock do not match.
  • In-rush data ingestion where one of the modules in the video pipeline cannot offer the necessary throughput to move the data at the expected rate.

In an example where CLK receiver signal drives some streaming full-raster, others are driven by a different clock domain signal, for example, CLK transmitter. Module B and Module C are both transferring data between them. Module C cannot keep up with the data rate imposed by Module B. The TREADY signal driven by Module C drops for a few clock cycles while it accepts the input data. For full-raster interfaces, any bubble inserted in between the TREADY and TVALID handshake process breaks the video timing data rate of the incoming data.

Figure 55. Streaming Full Raster Data Rate Mismatch: Backpressure Example

To accommodate a small amount of data-skew mismatching or in-rush data between streaming full-raster interfaces, compatible interfaces must provide an optional FIFO buffer. A FIFO buffer can accommodate bursts of data if and only if the data rate of the upstream full-raster video component is less than or equal to the data rate of the downstream components.

Figure 56. Streaming Full Raster Data Rate Matching: Full-Rate Case-Scenario

The figure shows an example where an AXI4-S compatible FIFO buffer is instantiated between the Modules B and C. This FIFO buffer temporally takes data that otherwise Module C misses allowing Module B to transfer the input data at the expected rate.

If the full-raster interface allows you to instantiate a FIFO buffer, the full-raster protocol enforces the addition of an overflow error signal to the corresponding processor register map of the IP using this video interface.

The full-raster protocol specifies and defines the way to exchange full-raster video data using a video stream interface. However, you must guarantee that the system can correctly process this data-skew mismatching or in-rush data ingestion between full-raster interfaces.

In your system, the data level in the FIFO buffer should always be above the underflow level and below the overflow threshold. This range is the FIFO data safe zone. An overflow can indicate that the receiver video interface driving the TREADY signal cannot ingest data at the correct data rate and starts creating excessive backpressure on the transmitter interface.

Figure 57. Example of a FIFO Data Safe Zone