2.2.1. TDATA Pixel Packing 2.2.2. RGB Pixel Packing 2.2.3. YCbCr 444 Pixel Packing 2.2.4. YCbCr 422 Pixel Packing 2.2.5. YCbCr 420 Pixel Packing 2.2.6. Four-Channel Video Pixel Packing 2.2.7. Packing with Multiple Pixels in Parallel 2.2.8. Multiple Pixels in Parallel and Empty Pixels 2.2.9. YCbCr 422 Video with Multiple Pixels in Parallel 2.2.10. Interlaced Fields
126.96.36.199. Register Update Packets
Intel FPGA streaming video register update packets allow individual video fields to individually receive different video processing, as you can inject register update packets between fields. Applications for register update packets include Dolby Vision, HDR10 or video processing applications that stream the control.
Figure 13. Register Update PacketThe figure shows register update packets.
A destination ID in bits 15 to 8 in the first beat of the register update packet allows the packet to be targeted at a particular destination IP. The second beat contains the address of a register to update. Beats 3 and 4, respectively, contain the least significant short word and most significant short word of the data you write.
Destination IDs 0xF0 to 0xFF are reserved.
Place register update packets between the end of field packet of the previous field and the image information packet of the field to which you apply the new control data.
Refer to Legal packet ordering rules and Packet ordering examples figures in Rules for Packets.
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