Intel FPGA Streaming Video Protocol Specification

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ID 683397
Date 7/25/2022
Public
Document Table of Contents

1. About the Intel FPGA Streaming Video Protocol

This protocol allows very high resolution and frame rate video processing. The protocol supports any number of pixels in parallel per clock cycle and video resolutions of up to 65536 by 65536 pixels.

An AMBA AXI4-Stream protocol underpins this architecture, which meets the needs of video and vision processing IPs, and allows easy interoperability with the latest Intel FPGA IP and other third-party IPs.

The AMBA AXI4-Stream protocol is natively supported in Platform Designer, allowing you to easily make connections between components.

The protocol allows interfacing to Intel FPGA video IPs or other AXI4-Stream compliant third-party video IPs.

Note:

A lite variant of the protocol specifies how video packets transport video data. The full variant adds transport of control packets. The full-raster protocol adds support for full-raster signalling.

The protocol runs on top of the AXI4-Stream wire-level protocol, with extensions for transporting control and video data.

The protocol moves color planes in parallel, with one or more pixels in parallel in one beat of data. You can specify as many pixels in parallel as the IPs can process using the protocol.

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