Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Bits per Color Sample Adapter Intel FPGA IP x
10.1. About the Bits per Color Sample Adapter IP 10.2. Bits per Color Sample Adapter IP Parameters 10.3. Bits per Color Sample Adapter IP Interfaces
10.1. About the Bits per Color Sample Adapter IP x
10.1.1. Bits per Color Sample Adapter IP Performance and Resources
11. Chroma Key Intel® FPGA IP x
11.1. About the Chroma Key IP 11.2. Chroma Key IP Parameters 11.3. Chroma Key IP Interfaces 11.4. Chroma Key Replacement 11.5. Chroma Key IP Registers 11.6. Chroma Key IP Software API
11.1. About the Chroma Key IP x
11.1.1. Chroma Key IP Performance and Resources
12. Chroma Resampler Intel® FPGA IP x
12.1. About the Chroma Resampler IP 12.2. Chroma Resampler IP Parameters 12.3. Chroma Resampler IP Functional Description 12.4. Chroma Resampler IP Registers 12.5. Chroma Resampler IP Software API
12.1. About the Chroma Resampler IP x
12.1.1. Chroma Resampler Performance and Resources
12.3. Chroma Resampler IP Functional Description x
12.3.1. Chroma Resampler IP Interfaces
13. Clipper Intel® FPGA IP x
13.1. About the Clipper IP 13.2. Clipper IP Parameters 13.3. Clipper IP Interfaces 13.4. Clipper IP Registers 13.5. Clipper IP Software API
13.1. About the Clipper IP x
13.1.1. Clipper IP Performance and Resources
14. Clocked Video Input Intel® FPGA IP x
14.1. About the Clocked Video Input IP 14.2. Initializing the Clocked Video Input IP 14.3. Clocked Video Input IP Parameters 14.4. Clocked Video Input IP Interfaces 14.5. Clocked Video Input IP Registers 14.6. Clocked Video Input IP Software API
14.1. About the Clocked Video Input IP x
14.1.1. Clocked Video Input IP Features 14.1.2. Clocked Video Input IP Performance and Resources
15. Clocked Video to Full-Raster Converter Intel® FPGA IP x
15.1. About the Clocked Video to Full-Raster Converter IP 15.2. Clocked Video to Full-Raster Converter Parameters 15.3. Clocked Video to Full-Raster Converter Block Description 15.4. Clocked Video Converter to Full-Raster IP Registers
15.1. About the Clocked Video to Full-Raster Converter IP x
15.1.1. Clocked Video to Full-Raster Converter Features 15.1.2. Clocked Video to Full-Raster Converter Performance and Resources
15.3. Clocked Video to Full-Raster Converter Block Description x
15.3.1. Clocked Video to Full-Raster Converter Interfaces
16. Clocked Video Output Intel® FPGA IP x
16.1. About the Clocked Video Output IP 16.2. Clocked Video Output IP Parameters 16.3. Clocked Video Output IP Functional Description 16.4. Clocked Video Output IP Interfaces 16.5. Clocked Video Output IP Registers 16.6. Clocked Video Output IP Software API
16.1. About the Clocked Video Output IP x
16.1.1. Clocked Video Output IP Performance and Resources 16.1.2. Clocked Video Output IP Features
17. Color Space Converter Intel® FPGA IP x
17.1. About the Color Space Converter IP 17.2. Color Space Converter IP Parameters 17.3. Color Space Converter IP Functional Description 17.4. Color Space Converter IP Registers 17.5. Color Space Converter IP Software API
17.1. About the Color Space Converter IP x
17.1.1. Color Space Converter IP Features 17.1.2. Color Space Converter IP Performance and Resources
17.3. Color Space Converter IP Functional Description x
17.3.1. Color Space Converter IP Interfaces
18. Deinterlacer Intel® FPGA IP x
18.1. About the Deinterlacer IP 18.2. Deinterlacer Parameters 18.3. Deinterlacer Interfaces 18.4. Deinterlacer IP Registers 18.5. Deinterlacer IP Software API
18.1. About the Deinterlacer IP x
18.1.1. Deinterlacer Performance and Resources
19. FIR Filter Intel® FPGA IP x
19.1. About the FIR Filter 19.2. FIR Filter Parameters 19.3. FIR Filter IP Operation 19.4. FIR Filter Interfaces 19.5. FIR Filter Registers 19.6. FIR Filter IP Software API
19.1. About the FIR Filter x
19.1.1. FIR Filter IP Performance and Resources
19.3. FIR Filter IP Operation x
19.3.1. FIR Filter Processing 19.3.2. FIR Filter Precision 19.3.3. FIR Coefficient Specification 19.3.4. FIR Filter Symmetry 19.3.5. Result to Output Data Type Conversion
19.3.4. FIR Filter Symmetry x
19.3.4.1. No Symmetry 19.3.4.2. Horizontal Symmetry 19.3.4.3. Vertical Symmetry 19.3.4.4. Horizontal and Vertical Symmetry 19.3.4.5. Diagonal Symmetry
20. Frame Cleaner Intel® FPGA IP x
20.1. About the Frame Cleaner IP 20.2. Frame Cleaner IP Parameters 20.3. Frame Cleaner IP Functional Description 20.4. Frame Cleaner IP Interfaces 20.5. Frame Cleaner IP Registers 20.6. Frame Cleaner IP Software API
20.1. About the Frame Cleaner IP x
20.1.1. Frame Cleaner IP Performance and Resources
21. Full-Raster to Clocked Video Converter Intel® FPGA IP x
21.1. About the Full-Raster to Clocked Video Converter 21.2. Full Raster to Clocked Video Converter Parameters 21.3. Full-Raster to Clocked Video Converter Block Description 21.4. Full-Raster to Clocked Video Converter Registers
21.1. About the Full-Raster to Clocked Video Converter x
21.1.1. Full-Raster to Clocked Video Converter Features 21.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
21.3. Full-Raster to Clocked Video Converter Block Description x
21.3.1. Full Raster to Clocked Video Converter Interfaces
22. Full-Raster to Streaming Converter Intel® FPGA IP x
22.1. About the Full-Raster to Streaming Converter IP 22.2. Full-Raster to Streaming Converter Parameters 22.3. Full-Raster to Streaming Converter Block Description
22.1. About the Full-Raster to Streaming Converter IP x
22.1.1. Full-Raster to Streaming Converter Features 22.1.2. Full-Raster to Streaming Converter Performance and Resources
22.3. Full-Raster to Streaming Converter Block Description x
22.3.1. Full-Raster to Streaming Converter Interfaces
23. Genlock Controller Intel® FPGA IP x
23.1. About the Genlock Controller IP 23.2. Genlock Controller IP Parameters 23.3. Genlock Controller IP Functional Description 23.4. Using Genlock Controller IP Software 23.5. Genlock Controller IP Registers 23.6. Genlock Controller IP Software API
23.1. About the Genlock Controller IP x
23.1.1. Genlock Controller IP Performance and Resources
23.3. Genlock Controller IP Functional Description x
23.3.1. Genlock Controller IP Interfaces
23.4. Using Genlock Controller IP Software x
23.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 23.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 23.4.3. Setting the VCXO hold over 23.4.4. Restarting the Genlock Controller IP 23.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 23.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 23.4.7. Disturbing a Reference Clock (a cable pull)
24. Generic Crosspoint Intel® FPGA IP x
24.1. About the Generic Crosspoint IP 24.2. Generic Crosspoint IP Parameters 24.3. Generic Crosspoint IP Interfaces 24.4. Generic Crosspoint IP Registers 24.5. Generic Crosspoint IP Software API
24.1. About the Generic Crosspoint IP x
24.1.1. Generic Crosspoint IP Features 24.1.2. Generic Crosspoint Performance and Resources
25. Genlock Signal Router Intel® FPGA IP x
25.1. About the Genlock Signal Router IP 25.2. Genlock Signal Router IP Parameters 25.3. Genlock Signal Router IP Interfaces 25.4. Genlock Signal Router IP Registers 25.5. Genlock Signal Router IP Software API
25.1. About the Genlock Signal Router IP x
25.1.1. Genlock Signal Router IP Features 25.1.2. Genlock Signal Router IP Performance and Resources
26. Guard Bands Intel® FPGA IP x
26.1. About the Guard Bands IP 26.2. Guard Bands IP Parameters 26.3. Guard Bands IP Interfaces 26.4. Guard Bands IP Registers 26.5. Guard Bands IP Software API
26.1. About the Guard Bands IP x
26.1.1. Guard Bands IP Performance and Resources
27. Interlacer Intel® FPGA IP x
27.1. About the Interlacer IP 27.2. Interlacer IP Parameters 27.3. Interlacer IP Functional Description 27.4. Interlacer IP Registers 27.5. Interlacer IP Software API
27.1. About the Interlacer IP x
27.1.1. Interlacer IP Performance and Resources
27.3. Interlacer IP Functional Description x
27.3.1. Interlacer IP Interfaces
28. Mixer Intel® FPGA IP x
28.1. About the Mixer IP 28.2. Mixer IP Parameters 28.3. Mixer IP Functional Description 28.4. Mixer IP Registers 28.5. Mixer IP Software API
28.1. About the Mixer IP x
28.1.1. Mixer IP Performance and Resources
28.3. Mixer IP Functional Description x
28.3.1. Mixer IP Interfaces
29. Pixels in Parallel Converter Intel® FPGA IP x
29.1. About the Pixels in Parallel Converter IP 29.2. Pixels in Parallel Converter IP Parameters 29.3. Pixels in Parallel Converter Interfaces 29.4. Pixels in Parallel Converter Registers 29.5. Pixels in Parallel Converter IP Software API
29.1. About the Pixels in Parallel Converter IP x
29.1.1. Pixels in Parallel Converter IP Performance and Resources
30. Scaler Intel® FPGA IP x
30.1. About the Scaler 30.2. Scaler IP Parameters 30.3. Scaler IP Functional Description 30.4. Scaler IP Registers 30.5. Scaler IP Software API
30.1. About the Scaler x
30.1.1. Scaler IP Performance and Resources
30.2. Scaler IP Parameters x
30.2.1. Scaler Maximum Resolution
30.3. Scaler IP Functional Description x
30.3.1. Coefficient Selection 30.3.2. Coefficient Quantization 30.3.3. Filter Behavior at Edge Boundaries 30.3.4. Partial Frame Scaling 30.3.5. 422 and 420 Chroma Sampled Data Scaling 30.3.6. Scaler IP Interfaces
30.3.1. Coefficient Selection x
30.3.1.1. Updating Scaler IP Runtime Coefficients
31. Stream Cleaner Intel® FPGA IP x
31.1. About the Stream Cleaner IP 31.2. Stream Cleaner IP Parameters 31.3. Stream Cleaner IP Functional Description
31.1. About the Stream Cleaner IP x
31.1.1. Stream Cleaner IP Performance and Resources
31.3. Stream Cleaner IP Functional Description x
31.3.1. Stream Cleaner IP Interfaces
32. Switch Intel® FPGA IP x
32.1. About the Switch IP 32.2. Switch IP Parameters 32.3. Switch IP Functional Description 32.4. Switch IP Registers 32.5. Switch IP Software API
32.1. About the Switch IP x
32.1.1. Switch IP Performance and Resources
32.3. Switch IP Functional Description x
32.3.1. Switch IP Latency 32.3.2. Switch IP Interfaces
33. Tone Mapping Operator Intel® FPGA IP x
33.1. About the Tone Mapping Operator IP 33.2. TMO IP Parameters 33.3. TMO IP Block Description 33.4. TMO IP Registers 33.5. TMO IP Software API
33.1. About the Tone Mapping Operator IP x
33.1.1. TMO IP Features 33.1.2. TMO IP Performance and Resource Utilization
33.3. TMO IP Block Description x
33.3.1. TMO IP Interfaces 33.3.2. TMO IP Latency
34. Test Pattern Generator Intel® FPGA IP x
34.1. About the Test Pattern Generator IP 34.2. Test Pattern Generator IP Parameters 34.3. Test Pattern Generator IP Functional Description 34.4. Test Pattern Generator IP Registers 34.5. Test Pattern Generator IP Software API
34.1. About the Test Pattern Generator IP x
34.1.1. Test Pattern Generator IP Performance and Resources
34.3. Test Pattern Generator IP Functional Description x
34.3.1. Test Pattern Generator IP Interfaces
35. Video and Vision Monitor Intel FPGA IP x
35.1. About the Video and Vision Monitor IP 35.2. Video and Vision Monitor IP Parameters 35.3. Video and Vision Monitor IP Functional Description 35.4. Video and Vision Monitor IP Registers 35.5. Video and Vision Monitor Software API
35.1. About the Video and Vision Monitor IP x
35.1.1. Video and Vision Monitor IP Performance and Resources
35.3. Video and Vision Monitor IP Functional Description x
35.3.1. Video and Vision Monitor IP Interfaces
36. Video Frame Buffer Intel® FPGA IP x
36.1. About the Video Frame Buffer IP 36.2. Video Frame Buffer IP Parameters 36.3. Video Frame Buffer IP Functional Description 36.4. Video Frame Buffer IP Registers 36.5. Video Frame Buffer IP Software API
36.1. About the Video Frame Buffer IP x
36.1.1. Video Frame Buffer Performance and Resources
36.3. Video Frame Buffer IP Functional Description x
36.3.1. Video Frame Buffer IP Interfaces
37. Video Frame Reader Intel FPGA IP x
37.1. About the Video Frame Reader IP 37.2. Video Frame Reader IP Parameters 37.3. Video Frame Reader IP Functional Description 37.4. Video Frame Reader IP Registers 37.5. Video Frame Reader IP Software API
37.1. About the Video Frame Reader IP x
37.1.1. Video Frame Reader IP Performance and Resources
37.3. Video Frame Reader IP Functional Description x
37.3.1. Video Frame Reader IP Interfaces
38. Video Frame Writer Intel FPGA IP x
38.1. About the Video Buffer Writer IP 38.2. Video Frame Writer IP Parameters 38.3. Video Frame Writer IP Functional Description 38.4. Video Frame Writer IP Registers 38.5. Video Frame Writer IP Software API
38.1. About the Video Buffer Writer IP x
38.1.1. Video Frame Writer IP Performance and Resources
38.3. Video Frame Writer IP Functional Description x
38.3.1. Video Frame Writer IP Interfaces
39. Video Streaming FIFO Intel® FPGA IP x
39.1. About the Video Streaming FIFO IP 39.2. Video Streaming FIFO IP Parameters 39.3. Video Streaming FIFO IP Interfaces
39.1. About the Video Streaming FIFO IP x
39.1.1. Video Streaming FIFO IP Performance and Resources
40. Video Timing Generator Intel® FPGA IP x
40.1. About the Video Timing Generator IP 40.2. Video Timing Generator IP Parameters 40.3. Video Timing Generator IP Functional Description 40.4. Video Timing Generator IP Interfaces 40.5. Video Timing Generator IP Registers 40.6. Video Timing Generator IP Software API
40.1. About the Video Timing Generator IP x
40.1.1. Video Timing Generator IP Features 40.1.2. Video Timing Generator IP Performance and Resources
41. Warp Intel® FPGA IP x
41.1. About the Warp IP 41.2. Warp IP Parameters 41.3. Warp IP Block Description 41.4. Warp IP Registers 41.5. Warp IP Software API
41.1. About the Warp IP x
41.1.1. Warp IP Features 41.1.2. Warp IP Performance and Resource Utilization
41.3. Warp IP Block Description x
41.3.1. Block Cache Tool 41.3.2. Warp IP Interfaces 41.3.3. Warp IP Latency 41.3.4. External Memory for Warp IP
41.5. Warp IP Software API x
41.5.1. Using Warp IP Software 41.5.2. Warp IP Software Code Examples
42. Design Security x
42.1. Memory Subsystems 42.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Bits per Color Sample Adapter Intel FPGA IP
11. Chroma Key Intel® FPGA IP
12. Chroma Resampler Intel® FPGA IP
13. Clipper Intel® FPGA IP
14. Clocked Video Input Intel® FPGA IP
15. Clocked Video to Full-Raster Converter Intel® FPGA IP
16. Clocked Video Output Intel® FPGA IP
17. Color Space Converter Intel® FPGA IP
18. Deinterlacer Intel® FPGA IP
19. FIR Filter Intel® FPGA IP
20. Frame Cleaner Intel® FPGA IP
21. Full-Raster to Clocked Video Converter Intel® FPGA IP
22. Full-Raster to Streaming Converter Intel® FPGA IP
23. Genlock Controller Intel® FPGA IP
24. Generic Crosspoint Intel® FPGA IP
25. Genlock Signal Router Intel® FPGA IP
26. Guard Bands Intel® FPGA IP
27. Interlacer Intel® FPGA IP
28. Mixer Intel® FPGA IP
29. Pixels in Parallel Converter Intel® FPGA IP
30. Scaler Intel® FPGA IP
31. Stream Cleaner Intel® FPGA IP
32. Switch Intel® FPGA IP
33. Tone Mapping Operator Intel® FPGA IP
34. Test Pattern Generator Intel® FPGA IP
35. Video and Vision Monitor Intel FPGA IP
36. Video Frame Buffer Intel® FPGA IP
37. Video Frame Reader Intel FPGA IP
38. Video Frame Writer Intel FPGA IP
39. Video Streaming FIFO Intel® FPGA IP
40. Video Timing Generator Intel® FPGA IP
41. Warp Intel® FPGA IP
42. Design Security
43. Document Revision History for Video and Vision Processing Suite User Guide

40.5. Video Timing Generator IP Registers

The processor interface is optional. You must turn it on at build time on the Build Parameters tab in the GUI. Unless stated, all registers are 32-bit wide.
Table 769.  External Processor Interface

The Video Timing Generator IP allows run-time configuration of parameters via an Avalon memory-mapped processor register interface.

Register Offset Access Description

Parameterization Registers

VID_PID 0x000 RO Read this register to retrieve the product ID
VERSION 0x004 RO Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build the IP.
NUM_PULSES 0x008 RO The number of additional output pulses generated by the Video Timing Generator.
OUTPUT_IS_CV 0x00c RO

When 1, the output is legacy Intel Clocked Video.

When 0, the output is a full-raster variant.
ALIGNED_ONLY 0x010 RO

When 1, the raster is restricted such that all timing parameters for the raster must be integer multiples of the number of pixels in parallel.

When 0, the timing parameters have no restrictions.

NUMBER_OF_COLOR_PLANES 0x014 RO The number of color planes per pixel.
PIXELS_IN_PARALLEL 0x018 RO The number of pixels per clock transferred on the AXI4-S buses.
BPS 0x01c RO The bits per video sample.
HSIZE 0x020 RO The number of bits to build the horizontal counters and comparators in the Video Timing Generator. Determines the maximum width of raster that the IP can generate.
VSIZE 0x024 RO The number of bits to build the vertical counters and comparators inside the Video Timing Generator. Determines the maximum height of raster that the IP can generate.
CPU_CLK_FREQ_HZ 0x028 RO The frequency, in Hz, of the processor interface clock.
BUILD_HARD_FRAME_LOCK 0x02c RO

If true, the Video Timing Generator includes the hard frame lock function.

If false, the Video Timing Generator cannot achieve a hard lock to an external reference.

BUILD_SOFT_FRAME_LOCK 0x030 RO

If true, the Video Timing Generator includes the soft frame lock function.

If false, the Video Timing Generator cannot achieve a soft lock to an external reference.

BUILD_VRR 0x034 RO

If true, the Video Timing Generator includes the variable refresh rate.

If false, the Video Timing Generator cannot generate a variable refresh rate.
Table 770.  Core Processor Register Description
Register Offset Access Description

Raster Timing Registers

REG_STATUS 0x140 RO Reserved
REG_COMMIT 0x144 RW Update internal parameters with new video standard.
REG_MODE 0x148 RW Control mode of operation.
REG_RESET_POS 0x14c RW Expected position of the start of frame input signal, relative to the raster
REG_TOTALS 0x150 RW Total height and width of the raster
REG_HB_END 0x154 RW First active pixel of a line
REG_V1B_POS 0x158 RW Start and end of vertical blanking for field 1
REG_V2B_POS 0x15c RW Start and end of vertical blanking for field 2
REG_FIELD_STARTS 0x160 RW First lines of field 1 and 2
REG_HS_POS 0x164 RW The start and end of horizontal sync
REG_V1S_START 0x168 RW The horizontal and vertical position of the start of the vertical sync for field 1
REG_V1S_END 0x16c RW The horizontal and vertical position of the end of the vertical sync for field 1
REG_V2S_START 0x170 RW The horizontal and vertical position of the start of the vertical sync for field 2
REG_V2S_END 0x174 RW The horizontal and vertical position of the end of the vertical sync for field 2
REG_JITTER_CONT 0x178 RW Timing parameters for the hard and soft frame locks
REG_BLACK_0 0x17c RW The initial value of black for this color plane
REG_BLACK_1 0x180 RW 116 The initial value of black for this color plane
REG_BLACK_2 0x184 RW 116 The initial value of black for this color plane
REG_BLACK_3 0x188 RW 116 The initial value of black for this color plane
REG_FRAME_COUNTS 0x18c RO Returns the total number of frames output, and the number of external frame starts received.
REG_FRAME_LENGTH 0x190 RO The number of video clocks between consecutive frame start input signals
REG_VTOTAL_ADJ 0x194 RO 117 The total height of the raster after adjustment for soft frame lock.
REG_VID_FREQ 0x198 RO The frequency of the video clock, in Hz.
REG_GENLOCK_STATS0 0x19c RO Diagnostics for hard and soft frame lock
REG_GENLOCK_STATS1 0x1a0 RO Diagnostics for soft frame lock.

Pulse and Toggle Timing Registers

REG_PULSE0_START 0x1c0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE0_END 0x1c4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE1_START 0x1c8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE1_END 0x1cc RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE2_START 0x1d0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE2_END 0x1d4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE3_START 0x1d8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE3_END 0x1dc RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE4_START 0x1e0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE4_END 0x1e4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE5_START 0x1e8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE5_END 0x1ec RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE6_START 0x1f0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE6_END 0x1f4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE7_START 0x1f8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE7_END 0x1fc RW 118 The horizontal and vertical position of the end of the pulse
Table 771.  REG_STATUS
Name Bits Attribute Description
Reserved 31:0 Rsvd Reserved
Table 772.  REG_COMMIT
Name Bits Attribute Description
Commit 0 WO Writing a 1 to this bit causes all uploaded processor parameters to be committed to the Video Timing Generators at the start of the next raster.
VidClkRunning 1 RO

1 indicates the video clock is running.

0 indicates the video clock is not running, or is unstable.
UpdateTimingRequest 2 RO

1 indicates the IP issues a commit, but is not completed. Ther commit logic has seen no start of raster.

0 indicates no commit is pending.

Table 773.  REG_MODE
Name Bits Attribute Description
Frame Start is Pulse 0 RW

Sets the type of signal for the frame start input

If 1, the input is a short pulse

If 0, the input is a per-frame toggle
Blank_n_Sync 1 RW

If 1, the IP generates blank timing

If 0, the IP generates sync timing
HardFrameLock 2 RW

If 1, the soft frame lock is false.

If 0, the soft frame lock is true
SoftFrameLock 3 RW

If 1, and the soft frame lock is false, soft frame lock is on.

If 0, soft frame lock is off.
VRR Enable 4 RW

If 1, variable refresh rate is on.

If 0, variable refresh rate is off.
VRR Line Mode 5 RW

If variable refresh rate is on, set to 1 to turn on the VVR Line Mode.

If set to 0, VVR Line Mode is off.

Reserved 31:6 RO Reserved
Table 774.  REG_RESET_POS
Name Bits Attribute Description
hReset hSize-1:0 RW The horizontal position, in pixels, of the expected frame start input signal
vReset 15+vSize:16 RW The vertical position, in lines, of the expected frame start input signal
Table 775.  REG_TOTALS
Name Bits Attribute Description
hTotal hSize-1:0 RW The width, in pixels, of the raster
vTotal 15+vSize:16 RW The height, in lines, of the raster
Table 776.  REG_HB_END
Name Bits Attribute Description
HB_END hSize-1:0 RW The first active pixel after the horizontal blanking.
Reserved 32:hSize RO Reserved
Table 777.  REG_V1B_POS
Name Bits Attribute Description
V1B Start vSize-1:0 RW The first line of vertical blanking for field 1
V1B End 15+vSize:16 RW The first active line of field 1
Table 778.  REG_V2B_POS
Name Bits Attribute Description
V2B Start vSize-1:0 RW

The first line of vertical blanking for field 2

For a progressive raster, set to -1
V2B End 15+vSize:16 RW

The first active line of field2

For a progressive raster, set to -1
Table 779.  REG_FIELD_STARTS
Name Bits Attribute Description
Field 1 Start vSize-1:0 RW The first line of field 1
Field 2 End 15+vSize:16 RW

The first line of field 2

For a progressive raster, set to -1
Table 780.  REG_HS_POS
Name Bits Attribute Description
HSync Start hSize-1:0 RW The first pixel of the horizontal sync
HSync End 15+hSize:16 RW The first pixel after the horizontal sync
Table 781.  REG_V1S_START
Name Bits Attribute Description
V1Sync hStart hSize-1:0 RW The first pixel of the vertical sync for field 1
V1Sync vStart 15+hSize:16 RW The first line of the vertical sync for field 1
Table 782.  REG_V1S_END
Name Bits Attribute Description
V1Sync hEnd hSize-1:0 RW The first pixel after the vertical sync for field 1
V1Sync vEnd 15+hSize:16 RW The last line of the vertical sync for field 1
Table 783.  REG_V2S_START
Name Bits Attribute Description
V2Sync hStart hSize-1:0 RW

The first pixel of the vertical sync for field 2

For a progressive raster, set to -1
V2Sync vStart 15+hSize:16 RW

The first line of the vertical sync for field 2

For a progressive raster, set to -1
Table 784.  REG_V2S_END
Name Bits Attribute Description
V2Sync hEnd hSize-1:0 RW

The first pixel after the vertical sync for field 2

For a progressive raster, set to -1
V2Sync vEnd 15+vSize:16 RW

The last line of the vertical sync for field 2

For a progressive raster, set to -1
Table 785.  REG_JITTER_CONT
Name Bits Attribute Description
Frame Start Max Jitter 7:0 RW

The number of video clock cycles either side of the position of the expected start of frame where an occurrence of the frame start input signal does not cause the raster to restart.

If the frame start input signal occurs more than this number of video clock cycles from the point where it is expected, the IP restarts the output raster.

Soft lock frame start ignore 15:8 RW

When you select True for Soft frame lock, this parameter specifies the number of lines where the frame start input signal is ignored.

When you select True for Soft frame lock, this parameter is not used.

Soft lock frame start adjust 23:16 RW

When you select True for Soft frame lock, this parameter specifies the total number of lines for soft lock, including the ignore lines.

When you select False for Soft frame lock, this parameter is not used.

Reserved 31:24 RO Reserved
Table 786.  REG_BLACK_0
Name Bits Attribute Description
BLACK_0 BIT_DEPTH-1:0 RW The initial value of black for this color plane
Table 787.  REG_BLACK_1
Name Bits Attribute Description
BLACK_1 BIT_DEPTH-1:0 RW

The initial value of black for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist
Table 788.  REG_BLACK_2
Name Bits Attribute Description
BLACK_2 BIT_DEPTH-1:0 RW

The initial value of black for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist
Table 789.  REG_BLACK_3
Name Bits Attribute Description
BLACK_3 BIT_DEPTH-1:0 RW

The initial value of black for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist
Table 790.  REG_FRAME_COUNTS
Name Bits Attribute Description
Start Counter 15:0 RO Counts occurrences of the Frame Start Input Signal.
Frame Counter 31:16 RO Counts number of frames generated.
Table 791.  REG_FRAME_LENGTH
Name Bits Attribute Description
Frame Length hSize+vSize-1:0 RO The number of video clocks per occurrence of the frame start input signal.
Table 792.  REG_VTOTAL_ADJ
Name Bits Attribute Description
vTotal_Adj vSize-1:0 RO The total number of lines per frame used by the soft frame lock.
Reserved 31:vSize RO Reserved.
Table 793.  REG_VID_FREQ
Name Bits Attribute Description
VidClkFreq 31:0 RO The frequency of the video clock, in Hz.
Table 794.  REG_GENLOCK_STATS0
Name Bits Attribute Description
Reset Count 15:0 RO

Counts the number of times the raster is reset by the frame start signal.

Normally static and only increments when the output standard is changed. If this value is constantly incrementing, it suggests the period of the frame start signal does not match the period of the output raster.

Stable Count 31:16 RO This increments every time the soft frame lock mechanism does not change the vTotal_adj value.
Table 795.   REG_GENLOCK_STATS1
Name Bits Attribute Description
vTotal Inc Counter 15:0 RO Increments every time the soft frame lock mechanism increments the vTotal_adj value.
vTotal Dec Counter 31:16 RO Increments every time the soft frame lock mechanism decrements the vTotal_adj value.
Table 796.  REG_PULSE0_START
Name Bits Attribute Description
Pulse 0 hStart hSize-1:0 RW

The first pixel of the pulse
Pulse 0 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 797.  REG_PULSE0_END
Name Bits Attribute Description
Pulse 0 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 0 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 798.  REG_PULSE1_START
Name Bits Attribute Description
Pulse 1 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 1 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 799.  REG_PULSE1_END
Name Bits Attribute Description
Pulse 1 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 1 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 800.  REG_PULSE2_START
Name Bits Attribute Description
Pulse 2 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 2 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 801.  REG_PULSE2_END
Name Bits Attribute Description
Pulse 2 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 2 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 802.  REG_PULSE3_START
Name Bits Attribute Description
Pulse 3 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 3 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 803.  REG_PULSE3_END
Name Bits Attribute Description
Pulse 3 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 3 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 804.  REG_PULSE4_START
Name Bits Attribute Description
Pulse 4 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 4 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 805.  REG_PULSE4_END
Name Bits Attribute Description
Pulse 4 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 4 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 806.   REG_PULSE5_START
Name Bits Attribute Description
Pulse 5 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 5 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 807.  REG_PULSE5_END
Name Bits Attribute Description
Pulse 5 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 5 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 808.  REG_PULSE6_START
Name Bits Attribute Description
Pulse 6 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 6 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 809.  REG_PULSE6_END
Name Bits Attribute Description
Pulse 6 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 6 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 810.  REG_PULSE7_START
Name Bits Attribute Description
Pulse 7 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 7 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 811.  REG_PULSE7_END
Name Bits Attribute Description
Pulse 7 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 7 vEnd 15+vSize:16 RW

The last line of the pulse.

119
116

This register is RO and returns 0x1234abcd if the color plane does not exist.

117

If Soft Mode is off, this register is undefined.

118

This register is RO and returns 0x1234abcd if the pulse does not exist. Refer to Build Parameter tab Number of pulses

119

This register is RO and returns 0x1234abcd if the pulse does not exist. Refer to the Build Parameter tab Number of pulses

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