Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Bits per Color Sample Adapter Intel FPGA IP x
10.1. About the Bits per Color Sample Adapter IP 10.2. Bits per Color Sample Adapter IP Parameters 10.3. Bits per Color Sample Adapter IP Interfaces
10.1. About the Bits per Color Sample Adapter IP x
10.1.1. Bits per Color Sample Adapter IP Performance and Resources
11. Chroma Key Intel® FPGA IP x
11.1. About the Chroma Key IP 11.2. Chroma Key IP Parameters 11.3. Chroma Key IP Interfaces 11.4. Chroma Key Replacement 11.5. Chroma Key IP Registers 11.6. Chroma Key IP Software API
11.1. About the Chroma Key IP x
11.1.1. Chroma Key IP Performance and Resources
12. Chroma Resampler Intel® FPGA IP x
12.1. About the Chroma Resampler IP 12.2. Chroma Resampler IP Parameters 12.3. Chroma Resampler IP Functional Description 12.4. Chroma Resampler IP Registers 12.5. Chroma Resampler IP Software API
12.1. About the Chroma Resampler IP x
12.1.1. Chroma Resampler Performance and Resources
12.3. Chroma Resampler IP Functional Description x
12.3.1. Chroma Resampler IP Interfaces
13. Clipper Intel® FPGA IP x
13.1. About the Clipper IP 13.2. Clipper IP Parameters 13.3. Clipper IP Interfaces 13.4. Clipper IP Registers 13.5. Clipper IP Software API
13.1. About the Clipper IP x
13.1.1. Clipper IP Performance and Resources
14. Clocked Video Input Intel® FPGA IP x
14.1. About the Clocked Video Input IP 14.2. Initializing the Clocked Video Input IP 14.3. Clocked Video Input IP Parameters 14.4. Clocked Video Input IP Interfaces 14.5. Clocked Video Input IP Registers 14.6. Clocked Video Input IP Software API
14.1. About the Clocked Video Input IP x
14.1.1. Clocked Video Input IP Features 14.1.2. Clocked Video Input IP Performance and Resources
15. Clocked Video to Full-Raster Converter Intel® FPGA IP x
15.1. About the Clocked Video to Full-Raster Converter IP 15.2. Clocked Video to Full-Raster Converter Parameters 15.3. Clocked Video to Full-Raster Converter Block Description 15.4. Clocked Video Converter to Full-Raster IP Registers
15.1. About the Clocked Video to Full-Raster Converter IP x
15.1.1. Clocked Video to Full-Raster Converter Features 15.1.2. Clocked Video to Full-Raster Converter Performance and Resources
15.3. Clocked Video to Full-Raster Converter Block Description x
15.3.1. Clocked Video to Full-Raster Converter Interfaces
16. Clocked Video Output Intel® FPGA IP x
16.1. About the Clocked Video Output IP 16.2. Clocked Video Output IP Parameters 16.3. Clocked Video Output IP Functional Description 16.4. Clocked Video Output IP Interfaces 16.5. Clocked Video Output IP Registers 16.6. Clocked Video Output IP Software API
16.1. About the Clocked Video Output IP x
16.1.1. Clocked Video Output IP Performance and Resources 16.1.2. Clocked Video Output IP Features
17. Color Space Converter Intel® FPGA IP x
17.1. About the Color Space Converter IP 17.2. Color Space Converter IP Parameters 17.3. Color Space Converter IP Functional Description 17.4. Color Space Converter IP Registers 17.5. Color Space Converter IP Software API
17.1. About the Color Space Converter IP x
17.1.1. Color Space Converter IP Features 17.1.2. Color Space Converter IP Performance and Resources
17.3. Color Space Converter IP Functional Description x
17.3.1. Color Space Converter IP Interfaces
18. Deinterlacer Intel® FPGA IP x
18.1. About the Deinterlacer IP 18.2. Deinterlacer Parameters 18.3. Deinterlacer Interfaces 18.4. Deinterlacer IP Registers 18.5. Deinterlacer IP Software API
18.1. About the Deinterlacer IP x
18.1.1. Deinterlacer Performance and Resources
19. FIR Filter Intel® FPGA IP x
19.1. About the FIR Filter 19.2. FIR Filter Parameters 19.3. FIR Filter IP Operation 19.4. FIR Filter Interfaces 19.5. FIR Filter Registers 19.6. FIR Filter IP Software API
19.1. About the FIR Filter x
19.1.1. FIR Filter IP Performance and Resources
19.3. FIR Filter IP Operation x
19.3.1. FIR Filter Processing 19.3.2. FIR Filter Precision 19.3.3. FIR Coefficient Specification 19.3.4. FIR Filter Symmetry 19.3.5. Result to Output Data Type Conversion
19.3.4. FIR Filter Symmetry x
19.3.4.1. No Symmetry 19.3.4.2. Horizontal Symmetry 19.3.4.3. Vertical Symmetry 19.3.4.4. Horizontal and Vertical Symmetry 19.3.4.5. Diagonal Symmetry
20. Frame Cleaner Intel® FPGA IP x
20.1. About the Frame Cleaner IP 20.2. Frame Cleaner IP Parameters 20.3. Frame Cleaner IP Functional Description 20.4. Frame Cleaner IP Interfaces 20.5. Frame Cleaner IP Registers 20.6. Frame Cleaner IP Software API
20.1. About the Frame Cleaner IP x
20.1.1. Frame Cleaner IP Performance and Resources
21. Full-Raster to Clocked Video Converter Intel® FPGA IP x
21.1. About the Full-Raster to Clocked Video Converter 21.2. Full Raster to Clocked Video Converter Parameters 21.3. Full-Raster to Clocked Video Converter Block Description 21.4. Full-Raster to Clocked Video Converter Registers
21.1. About the Full-Raster to Clocked Video Converter x
21.1.1. Full-Raster to Clocked Video Converter Features 21.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
21.3. Full-Raster to Clocked Video Converter Block Description x
21.3.1. Full Raster to Clocked Video Converter Interfaces
22. Full-Raster to Streaming Converter Intel® FPGA IP x
22.1. About the Full-Raster to Streaming Converter IP 22.2. Full-Raster to Streaming Converter Parameters 22.3. Full-Raster to Streaming Converter Block Description
22.1. About the Full-Raster to Streaming Converter IP x
22.1.1. Full-Raster to Streaming Converter Features 22.1.2. Full-Raster to Streaming Converter Performance and Resources
22.3. Full-Raster to Streaming Converter Block Description x
22.3.1. Full-Raster to Streaming Converter Interfaces
23. Genlock Controller Intel® FPGA IP x
23.1. About the Genlock Controller IP 23.2. Genlock Controller IP Parameters 23.3. Genlock Controller IP Functional Description 23.4. Using Genlock Controller IP Software 23.5. Genlock Controller IP Registers 23.6. Genlock Controller IP Software API
23.1. About the Genlock Controller IP x
23.1.1. Genlock Controller IP Performance and Resources
23.3. Genlock Controller IP Functional Description x
23.3.1. Genlock Controller IP Interfaces
23.4. Using Genlock Controller IP Software x
23.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 23.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 23.4.3. Setting the VCXO hold over 23.4.4. Restarting the Genlock Controller IP 23.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 23.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 23.4.7. Disturbing a Reference Clock (a cable pull)
24. Generic Crosspoint Intel® FPGA IP x
24.1. About the Generic Crosspoint IP 24.2. Generic Crosspoint IP Parameters 24.3. Generic Crosspoint IP Interfaces 24.4. Generic Crosspoint IP Registers 24.5. Generic Crosspoint IP Software API
24.1. About the Generic Crosspoint IP x
24.1.1. Generic Crosspoint IP Features 24.1.2. Generic Crosspoint Performance and Resources
25. Genlock Signal Router Intel® FPGA IP x
25.1. About the Genlock Signal Router IP 25.2. Genlock Signal Router IP Parameters 25.3. Genlock Signal Router IP Interfaces 25.4. Genlock Signal Router IP Registers 25.5. Genlock Signal Router IP Software API
25.1. About the Genlock Signal Router IP x
25.1.1. Genlock Signal Router IP Features 25.1.2. Genlock Signal Router IP Performance and Resources
26. Guard Bands Intel® FPGA IP x
26.1. About the Guard Bands IP 26.2. Guard Bands IP Parameters 26.3. Guard Bands IP Interfaces 26.4. Guard Bands IP Registers 26.5. Guard Bands IP Software API
26.1. About the Guard Bands IP x
26.1.1. Guard Bands IP Performance and Resources
27. Interlacer Intel® FPGA IP x
27.1. About the Interlacer IP 27.2. Interlacer IP Parameters 27.3. Interlacer IP Functional Description 27.4. Interlacer IP Registers 27.5. Interlacer IP Software API
27.1. About the Interlacer IP x
27.1.1. Interlacer IP Performance and Resources
27.3. Interlacer IP Functional Description x
27.3.1. Interlacer IP Interfaces
28. Mixer Intel® FPGA IP x
28.1. About the Mixer IP 28.2. Mixer IP Parameters 28.3. Mixer IP Functional Description 28.4. Mixer IP Registers 28.5. Mixer IP Software API
28.1. About the Mixer IP x
28.1.1. Mixer IP Performance and Resources
28.3. Mixer IP Functional Description x
28.3.1. Mixer IP Interfaces
29. Pixels in Parallel Converter Intel® FPGA IP x
29.1. About the Pixels in Parallel Converter IP 29.2. Pixels in Parallel Converter IP Parameters 29.3. Pixels in Parallel Converter Interfaces 29.4. Pixels in Parallel Converter Registers 29.5. Pixels in Parallel Converter IP Software API
29.1. About the Pixels in Parallel Converter IP x
29.1.1. Pixels in Parallel Converter IP Performance and Resources
30. Scaler Intel® FPGA IP x
30.1. About the Scaler 30.2. Scaler IP Parameters 30.3. Scaler IP Functional Description 30.4. Scaler IP Registers 30.5. Scaler IP Software API
30.1. About the Scaler x
30.1.1. Scaler IP Performance and Resources
30.2. Scaler IP Parameters x
30.2.1. Scaler Maximum Resolution
30.3. Scaler IP Functional Description x
30.3.1. Coefficient Selection 30.3.2. Coefficient Quantization 30.3.3. Filter Behavior at Edge Boundaries 30.3.4. Partial Frame Scaling 30.3.5. 422 and 420 Chroma Sampled Data Scaling 30.3.6. Scaler IP Interfaces
30.3.1. Coefficient Selection x
30.3.1.1. Updating Scaler IP Runtime Coefficients
31. Stream Cleaner Intel® FPGA IP x
31.1. About the Stream Cleaner IP 31.2. Stream Cleaner IP Parameters 31.3. Stream Cleaner IP Functional Description
31.1. About the Stream Cleaner IP x
31.1.1. Stream Cleaner IP Performance and Resources
31.3. Stream Cleaner IP Functional Description x
31.3.1. Stream Cleaner IP Interfaces
32. Switch Intel® FPGA IP x
32.1. About the Switch IP 32.2. Switch IP Parameters 32.3. Switch IP Functional Description 32.4. Switch IP Registers 32.5. Switch IP Software API
32.1. About the Switch IP x
32.1.1. Switch IP Performance and Resources
32.3. Switch IP Functional Description x
32.3.1. Switch IP Latency 32.3.2. Switch IP Interfaces
33. Tone Mapping Operator Intel® FPGA IP x
33.1. About the Tone Mapping Operator IP 33.2. TMO IP Parameters 33.3. TMO IP Block Description 33.4. TMO IP Registers 33.5. TMO IP Software API
33.1. About the Tone Mapping Operator IP x
33.1.1. TMO IP Features 33.1.2. TMO IP Performance and Resource Utilization
33.3. TMO IP Block Description x
33.3.1. TMO IP Interfaces 33.3.2. TMO IP Latency
34. Test Pattern Generator Intel® FPGA IP x
34.1. About the Test Pattern Generator IP 34.2. Test Pattern Generator IP Parameters 34.3. Test Pattern Generator IP Functional Description 34.4. Test Pattern Generator IP Registers 34.5. Test Pattern Generator IP Software API
34.1. About the Test Pattern Generator IP x
34.1.1. Test Pattern Generator IP Performance and Resources
34.3. Test Pattern Generator IP Functional Description x
34.3.1. Test Pattern Generator IP Interfaces
35. Video and Vision Monitor Intel FPGA IP x
35.1. About the Video and Vision Monitor IP 35.2. Video and Vision Monitor IP Parameters 35.3. Video and Vision Monitor IP Functional Description 35.4. Video and Vision Monitor IP Registers 35.5. Video and Vision Monitor Software API
35.1. About the Video and Vision Monitor IP x
35.1.1. Video and Vision Monitor IP Performance and Resources
35.3. Video and Vision Monitor IP Functional Description x
35.3.1. Video and Vision Monitor IP Interfaces
36. Video Frame Buffer Intel® FPGA IP x
36.1. About the Video Frame Buffer IP 36.2. Video Frame Buffer IP Parameters 36.3. Video Frame Buffer IP Functional Description 36.4. Video Frame Buffer IP Registers 36.5. Video Frame Buffer IP Software API
36.1. About the Video Frame Buffer IP x
36.1.1. Video Frame Buffer Performance and Resources
36.3. Video Frame Buffer IP Functional Description x
36.3.1. Video Frame Buffer IP Interfaces
37. Video Frame Reader Intel FPGA IP x
37.1. About the Video Frame Reader IP 37.2. Video Frame Reader IP Parameters 37.3. Video Frame Reader IP Functional Description 37.4. Video Frame Reader IP Registers 37.5. Video Frame Reader IP Software API
37.1. About the Video Frame Reader IP x
37.1.1. Video Frame Reader IP Performance and Resources
37.3. Video Frame Reader IP Functional Description x
37.3.1. Video Frame Reader IP Interfaces
38. Video Frame Writer Intel FPGA IP x
38.1. About the Video Buffer Writer IP 38.2. Video Frame Writer IP Parameters 38.3. Video Frame Writer IP Functional Description 38.4. Video Frame Writer IP Registers 38.5. Video Frame Writer IP Software API
38.1. About the Video Buffer Writer IP x
38.1.1. Video Frame Writer IP Performance and Resources
38.3. Video Frame Writer IP Functional Description x
38.3.1. Video Frame Writer IP Interfaces
39. Video Streaming FIFO Intel® FPGA IP x
39.1. About the Video Streaming FIFO IP 39.2. Video Streaming FIFO IP Parameters 39.3. Video Streaming FIFO IP Interfaces
39.1. About the Video Streaming FIFO IP x
39.1.1. Video Streaming FIFO IP Performance and Resources
40. Video Timing Generator Intel® FPGA IP x
40.1. About the Video Timing Generator IP 40.2. Video Timing Generator IP Parameters 40.3. Video Timing Generator IP Functional Description 40.4. Video Timing Generator IP Interfaces 40.5. Video Timing Generator IP Registers 40.6. Video Timing Generator IP Software API
40.1. About the Video Timing Generator IP x
40.1.1. Video Timing Generator IP Features 40.1.2. Video Timing Generator IP Performance and Resources
41. Warp Intel® FPGA IP x
41.1. About the Warp IP 41.2. Warp IP Parameters 41.3. Warp IP Block Description 41.4. Warp IP Registers 41.5. Warp IP Software API
41.1. About the Warp IP x
41.1.1. Warp IP Features 41.1.2. Warp IP Performance and Resource Utilization
41.3. Warp IP Block Description x
41.3.1. Block Cache Tool 41.3.2. Warp IP Interfaces 41.3.3. Warp IP Latency 41.3.4. External Memory for Warp IP
41.5. Warp IP Software API x
41.5.1. Using Warp IP Software 41.5.2. Warp IP Software Code Examples
42. Design Security x
42.1. Memory Subsystems 42.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Bits per Color Sample Adapter Intel FPGA IP
11. Chroma Key Intel® FPGA IP
12. Chroma Resampler Intel® FPGA IP
13. Clipper Intel® FPGA IP
14. Clocked Video Input Intel® FPGA IP
15. Clocked Video to Full-Raster Converter Intel® FPGA IP
16. Clocked Video Output Intel® FPGA IP
17. Color Space Converter Intel® FPGA IP
18. Deinterlacer Intel® FPGA IP
19. FIR Filter Intel® FPGA IP
20. Frame Cleaner Intel® FPGA IP
21. Full-Raster to Clocked Video Converter Intel® FPGA IP
22. Full-Raster to Streaming Converter Intel® FPGA IP
23. Genlock Controller Intel® FPGA IP
24. Generic Crosspoint Intel® FPGA IP
25. Genlock Signal Router Intel® FPGA IP
26. Guard Bands Intel® FPGA IP
27. Interlacer Intel® FPGA IP
28. Mixer Intel® FPGA IP
29. Pixels in Parallel Converter Intel® FPGA IP
30. Scaler Intel® FPGA IP
31. Stream Cleaner Intel® FPGA IP
32. Switch Intel® FPGA IP
33. Tone Mapping Operator Intel® FPGA IP
34. Test Pattern Generator Intel® FPGA IP
35. Video and Vision Monitor Intel FPGA IP
36. Video Frame Buffer Intel® FPGA IP
37. Video Frame Reader Intel FPGA IP
38. Video Frame Writer Intel FPGA IP
39. Video Streaming FIFO Intel® FPGA IP
40. Video Timing Generator Intel® FPGA IP
41. Warp Intel® FPGA IP
42. Design Security
43. Document Revision History for Video and Vision Processing Suite User Guide

6. Video and Vision Processing IPs Software Programming Model

Most video and vision processing IPs are configurable at run-time. Memory-mapped run-time control interfaces expose a set of control registers to change the processing behavior and status registers to query the states of the processing functions. The set of available registers and the width in binary bits of each register varies with each control interface. You must assume that writable control registers and readable registers power up in an undefined state.

HAL Device Drivers for Nios II SBT

For software control and run-time reconfiguration, the Intel video and vision processing IPs have an associated software driver. The video IPs do not fit any of the generic device models provided by the Nios II HAL. Consequently, the bare-metal drivers only provide partial HAL support with a few dedicated accessor functions to the control and status registers. The video functions cannot be accessed indirectly through the generic HAL API or the ANSI C standard library.

Using these drivers in your application is optional. If you do not use drivers, Intel recommends you use the definitions provided by the register header files to control the IP components (*_regs.h) and avoid using unnamed constants and addresses to access the run-time register map from your application.

Refer to the Nios® II Software Developer's Handbook to get started with the Nios® II development tools.

Common Software API

Many Intel video and vision processing IPs expose a register map with common registers located at the same location (refer to the Video and Vision Processing Registers. To limit code footprint, many video and vision processing device structures (C struct) include a common device structure as their first member. This shared base allows the definition of a set of common functions to query the VID_PID and VERSION registers, respectively at addresses 0x0000 and 0x0004, and the set of IMG_INFO registers in the range 0x0120-0x013C.

Common API reference

Register definition header file: intel_vvp_core_regs.h

Include file: intel_vvp_core.h

Table 9.  Common API reference
Name Description
intel_vvp_core_init Initialize the instance.
intel_vvp_core_get_vendor_id Returns the vendor ID.
intel_vvp_core_get_product_id Returns the product ID.
intel_vvp_core_get_qpds_major Returns the version major number.
intel_vvp_core_get_qpds_update Returns the version update number.
intel_vvp_core_get_qpds_patch Returns the version patch number.
intel_vvp_core_get_register_map_version Returns the version number of the register map.
intel_vvp_core_get_img_info_width Returns the width read from the IMG_INFO_WIDTH register.
intel_vvp_core_get_img_info_height Returns the height read from the IMG_INFO_HEIGHT register.
intel_vvp_core_get_img_info_interlace Returns the interlace nibble read from the IMG_INFO_INTERLACE register.
intel_vvp_core_get_img_info_colorspace Returns the colorspace code read from the IMG_INFO_COLORSPACE register.
intel_vvp_core_get_img_info_subsampling Returns the subsampling code read from the IMG_INFO_SUBSAMPLING register.
intel_vvp_core_get_img_info_cositing Returns the cositing code read from the IMG_INFO_COSITING register.
intel_vvp_core_get_img_info_field_count Returns the field count code read from the IMG_INFO_FIELD_COUNT register.
intel_vvp_core_set_img_info_width Writes a width to the IMG_INFO_WIDTH register.
intel_vvp_core_set_img_info_height Writes a height to the IMG_INFO_HEIGHT register.
intel_vvp_core_set_img_info_interlace Writes an interlace nibble to the IMG_INFO_INTERLACE register.
intel_vvp_core_set_img_info_colorspace Writes a colorspace code to the IMG_INFO_COLORSPACE register.
intel_vvp_core_set_img_info_subsampling Writes a subsampling code to the IMG_INFO_SUBSAMPLING register.
intel_vvp_core_set_img_info_cositing Writes a cositing code to the IMG_INFO_COSITING register.

intel_vvp_core_init

Prototype 
 eIntelVvpCoreErrors intel_vvp_core_init(intel_vvp_core_instance *instance, intel_vvp_core_base base, uint16_t expected_product_id);
Description

Initializes the common members intel_vvp_core_instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match. Otherwise, the function proceeds to read and store the version numbers in the second register

Arguments

instance – pointer to the intel_vvp_core software driver instance structure

base – base address of the register map

expected_product_id – the expected product id

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the expectation

kIntelVvpCoreInstanceErr if the instance is a null pointer

intel_vvp_core_get_vendor_id

Prototype 
uint16_t intel_vvp_core_get_vendor_id(void *instance);
Description

Query the vendor_id of an initialized instance

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the vendor_id field in the intel_vvp_core_instance instance

intel_vvp_core_get_product_id

Prototype 
uint16_t intel_vvp_core_get_product_id(void *instance);
Description

Query the product _id of an initialized instance

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the product_id field in the intel_vvp_core_instance instance

intel_vvp_core_get_qpds_major

Prototype 
uint8_t intel_vvp_core_get_qpds_major(void *instance);
Description

Query the major version number of an instance. The instance must have been initialized successfully.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the major version number field in the intel_vvp_core_instance instance

intel_vvp_core_get_qpds_update

Prototype 
uint8_t intel_vvp_core_get_qpds_ update(void *instance);
Description

Query the minor version number of an instance. The instance must have been initialized successfully.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the update (minor) version number field in the intel_vvp_core_instance instance

intel_vvp_core_get_qpds_patch

Prototype 
uint8_t intel_vvp_core_get_qpds_patch(void *instance);
Description

Query the patch version number of an instance. The instance must have been initialized successfully.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the patch (build) version number field in the intel_vvp_core_instance instance

intel_vvp_core_get_register_map_version

Prototype 
uint8_t intel_vvp_core_get_register_map_version(void *instance);
Description

Query the register map version number of an instance. The instance must have been initialized successfully.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the register map version number field in the intel_vvp_core_instance instance

intel_vvp_core_get_img_info_width

Prototype 
uint32_t intel_vvp_core_get_img_info_width(void *instance);
Description

Read the IMG_INFO_WIDTH register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info width register

intel_vvp_core_get_img_info_height

Prototype 
uint32_t intel_vvp_core_get_img_info_height(void *instance);
Description

Read the IMG_INFO_HEIGHT register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info height register

intel_vvp_core_get_img_info_interlace

Prototype 
uint8_t intel_vvp_core_get_img_info_interlace(void *instance);
Description

Read the IMG_INFO_INTERLACE register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info interlace register

intel_vvp_core_get_img_info_colorspace

Prototype 
uint8_t intel_vvp_core_get_img_info_colorspace(void *instance);
Description

Read the IMG_INFO_COLORSPACE register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info colorspace register

intel_vvp_core_get_img_info_subsampling

Prototype 
uint8_t intel_vvp_core_get_img_info_subsampling(void *instance);
Description

Read the IMG_INFO_SUBSAMPLING register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info subsampling register

intel_vvp_core_get_img_info_cositing

Prototype 
uint8_t intel_vvp_core_get_img_info_cositing(void *instance);
Description

Read the IMG_INFO_COSITING register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info cositing register

intel_vvp_core_get_img_info_field_count

Prototype 
uint16_t intel_vvp_core_get_img_info_field_count(void *instance);
Description

Read the IMG_INFO_FIELD_COUNT register of an instance. The instance must have been initialized successfully and the register readable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

Returns

the value returned from a read to the image info field count register

intel_vvp_core_set_img_info_width

Prototype 
eIntelVvpCoreErrors intel_vvp_core_set_img_info_width(void *instance, uint32_t width);
Description

Write a new width to the IMG_INFO_WIDTH register of an instance. The instance must have been initialized successfully and the register writable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

width – new width

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

intel_vvp_core_set_img_info_height

Prototype 
eIntelVvpCoreErrors intel_vvp_core_set_img_info_height(void *instance, uint32_t height);
Description

Write a new height to the IMG_INFO_HEIGHT register of an instance. The instance must have been initialized successfully and the register writable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

height – new height

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

intel_vvp_core_set_img_info_interlace

Prototype 
eIntelVvpCoreErrors intel_vvp_core_set_img_info_interlace(void *instance, uint8_t height);
Description

Write a new interlace to the IMG_INFO_INTERLACE register of an instance. The instance must have been initialized successfully and the register writable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

height – new height

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

intel_vvp_core_set_img_info_colorspace

Prototype 
eIntelVvpCoreErrors intel_vvp_core_set_img_info_colorpsace (void *instance, uint8_t colorspace);
Description

Write a new colorspace to the IMG_INFO_COLORSPACE register of an instance. The instance must have been initialized successfully and the register writable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

colorspace – new colorspace

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

intel_vvp_core_set_img_info_subsampling

Prototype 
eIntelVvpCoreErrors intel_vvp_core_set_img_info_subsampling(void *instance, uint8_t subsampling);
Description

Write a new subsampling to the IMG_INFO_SUBSAMPLING register of an instance. The instance must have been initialized successfully and the register writable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

subsampling – new subsampling

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

intel_vvp_core_set_img_info_cositing

Prototype 
eIntelVvpCoreErrors intel_vvp_core_set_img_info_cositing (void *instance, uint8_t cositing);
Description

Write a new cositing to the IMG_INFO_COSITING register of an instance. The instance must have been initialized successfully and the register writable.

Arguments

instance – pointer to the initialized intel_vvp_core software driver instance structure or any software driver structure derived from it

cositing – new cositing

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

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