3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
Control and Image Information Packets
The Avalon streaming video protocol indicates control packets with the value 0xf in the low nibble of the first beat of the transaction. The control packet payload is then packed over subsequent beats into the low nibbles of each byte, across the whole width of the data bus. The Intel FPGA streaming video protocol indicates image information packets by setting tuser and 0x0 in the low 5 bits of the first beat. The protocol uses the remaining 11 bits of the first beat and the low 16 bits of subsequent beats to pack the remainder of the image information control packet.
Avalon streaming video carries data for the width field of the control packets in 4 nibbles spread across multiple bytes and often over multiple beats on the bus (w3:w0 in the figure). The Intel FPGA streaming video protocol always contains the 16 width field bits in the second beat of the transaction (w3:w0 in cycle 3 in the figure). Both protocols process the height field in these ways.
Interlace nibble codes have the same semantics in both protocols. Avalon streaming video carries interface nibble codes in the low nibble of the last byte of the packet. Intel FPGA streaming video packs them in positions 8 down to 5 of the first beat of the packet.
The Avalon streaming video protocol makes use of the Avalon streaming empty signal to indicate any empty symbols in the last beat. The Intel FPGA streaming video protocol does not use the AXI4-Stream TKEEP or TSRB signals.
Data packets in the Avalon streaming video protocol represent one entire field or frame of video. The Intel FPGA streaming video protocol transports each line of video as individual data packet. Data packets are also ready latency 1 in the Avalon streaming video protocol.
The protocols have other differences for pixel packing and empty symbols. The protocol converter IP manages these differences, so you do not need to understand the difference between the two standards.