2.1. Video and Vision Processing IP Evaluation Time-out Behavior
You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel FPGA IP Evaluation Mode, the IP only generates a time-limited device programming file ( <projectname>_time_limited.sof) that expires at the time limit.
All IPs in a device time out simultaneously when the most restrictive evaluation time is reached. If a design has more than one IP, the time-out behavior of the other IP may mask the time-out behavior of a specific IP.
When the evaluation time expires, the video and vision processing IP stops working.