Visible to Intel only — GUID: wwp1667813281693
Ixiasoft
Visible to Intel only — GUID: wwp1667813281693
Ixiasoft
23.5. Genlock Controller IP Registers
Offset | Register | Access | Description |
---|---|---|---|
Parameterization Registers | |||
0x000 | VID PID | RO | Read this register to retrieve clocked video input product ID. This register always returns 0x6FA7_0170. |
0x004 | Version number | RO | Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build this IP. |
0x008 to 0x00C |
Reserved | - | Reserved register area. |
0x010 | CPU clock frequency | RO | Read this register to retrieve the value for the CPU clock frequency in Hz. |
0x014 | Number of reference clock | RO | Read this register to retrieve the value for the number of input reference clocks used by this IP. |
0x018 | Difference value delta size | RO | Read this value to retrieve the value for the number of bits this IP uses to calculate the phase or frequency error between two samples. |
0x01C | Difference value size | RO | Read this value to retrieve the value for the number of bits this IP uses to calculate the phase or frequency error |
0x020 | Sample period counter size | RO | Read this register to retrieve the number of bits this IP uses to generate a sample period counter |
0x024 | LPF to DAC LSB position | RO | Read this register to retrieve the position of the LSBs that the IP ignores to calculate the error. |
0x028 | DAC resolution | RO | Read this register to retrieve the number of bits this IP uses to set the DAC resolution logic |
0x02C | PWM Output Clock Divider Value | RO | Read this register to retrieve the exact value used to divide the clock generating the PWM output pulse |
0x030 | Derivative enable | RO | Read this register to check if the derivate logic for this IP is on |
0x034 | LPF Mode | RO | Read this register to retrieve the exact mode of operation for the low pass filter |
0x038 | Proportional gain mode | RO | Read this register to retrieve the exact mode of operation for the proportional gain |
0x03C | Integral gain mode | RO | Read this register to retrieve the exact mode of operation for the integral gain |
0x040 | Derivative gain mode | RO | Read this register to retrieve the exact mode of operation for the derivative gain |
0x044 | VCXO Lock Confidence Counter Size | RO | Read this register to retrieve the number of bits this IP uses to generate a confidence lock counter |
0x048 | Enable Debug | RO | Read this register to check if the debugging logic for this IP is on |
Core Specific Registers | |||
0x148 | PFD Control | RW | This register configures the phase and frequency detector logic |
0x14C | PFD Status | RO | This register provides debug information about the phase and frequency detector logic |
0x150 | LPF Control 1 | RW | This register configures the LPF logic |
0x154 | LPF Control 2 | RW | This register configures the LPF logic |
0x158 | LPF Status | RO | This register provides debug information about the LPF logic |
0x15C | DAC Control | RW | This register configures the DAC control logic |
0x160 | DAC Status | RO | This register provides debug information about the DAC control logic |
0x164 | LPF Control 3 | RW | This register configures the LPF logic |
0x168 | Clock Debug Status 1 | RO | This register provides debug information about the VCXO clock frequency |
0x16C | Clock Debug Status 2 | RO | This register provides debug information about the Ref0 clock frequency |
0x170 | Clock Debug Status 3 | RO | This register provides debug information about the Ref1 clock frequency |
0x174 | Clock Debug Status 4 | RO | This register provides debug information about the Ref2 clock frequency |
0x178 | Clock Debug Status 5 | RO | This register provides debug information about the Ref3 clock frequency |
0x17C | PFD Debug Status | RO | This register provides debug information about the PFD accumulated error |
0x180 | Profiler Control | RW | This register configures the genclok profiler |
0x184 | Profiler Error Mapping 1 | RW | This register allows define a genlock profile error region |
0x188 | Profiler Error Mapping 2 | RW | This register allows define a genlock profile error region |
0x18C | Profiler Pixel Counter | RO | This register provides pixel count information gathered by the genlock profiler module |
0x190 | Profiler Jitter Sample | RO | This register provides jitter information gathered by the genlock profiler module |
0x194 | Profiler Statistics | RO | This register provides statistics information gathered by the genlock profiler module |
0x198 to 0x1A0 | Reserved | - | Reserved register area |
0x1A4 | Tx Rx Ref0 Clock Ratio | RW | If Ref0 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0 |
0x1A8 | Tx Rx Ref1 Clock Ratio | RW | If Ref1 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0 |
0x1AC | Tx Rx Ref2 Clock Ratio | RW | If Ref2 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0 |
0x1B0 | Tx Rx Ref3 Clock Ratio | RW | If Ref3 clock frequency is greater than VCXO clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0 |
0x1B4 | Tx Rx VCXO Clock Ratio | RW | If VCXO clock frequency is greater than reference clock frequency, this register sets the ratio between the two clocks. Otherwise set this register to 1.0 |
Register Bit Descriptions
Bits | Name | Description |
---|---|---|
0 | Enable |
|
3:2 | Ref Clock Switch Selection | Determines the reference clock for VCXO tracking:
Clock selection should only select clocks that exist in the design and ideally are running. |
7:4 | Ref Clock Reset | A 4-bit wide vector where each bit corresponds to an input reference clock (bit 4 = ref0_clk and bit 7 = ref3_clk). A 1 puts that reference places clock counter into reset and out of reset when you write, with bit 12 before you enable the PFD. |
12 | VCXO Clock Reset | A ‘1’ puts the VCXO clock counter into reset and out of reset when you write ‘0’. Set this bit when you reset the corresponding Ref Clock Reset required for tracking against. |
31:16 | Output Update Period MSBS | Defines the top 16 MSB of the output update period counter. The LSB are defined by the C_ERR_UPDATE_BITS at build and is the duration of error updates from the PFD to the LPF (and subsequently the DAC). Set up this value before you use the Enable bit. |
Bits | Name | Description |
---|---|---|
3:0 | Ref Clock Running | A 4 bits vector where each bit corresponds to an input reference clock (bit 0 = ref0_clk and bit 3 = ref3_clk) to indicate that the reference clock appears to be running. Running is based on samples the IP takes against the VCXO clock. If C_ENABLE_DEBUG>0, further clock measure registers are available. |
7:4 | Ref Clock Stopped | A 4 bits vector where each bit corresponds to an input reference clock (bit 0 = ref0_clk and bit 3 = ref3_clk) to indicate that the reference clock stops changing over the sampling period. These bits are sticky and only reset following an algorithm restart sequence. If the clock that dies is the current selected reference clock, the PFD does not update any further error changes to the LPF. The IP requires a restart sequence using either another reference clock or the same reference clock if it returns. The output disabled status is indicated in bit 9. |
8 | Overflow | Indicates an overflow in the difference between the internal tracking counters. An overflow is a serious error and the VCXO can be tracking anywhere. This bit only resets after a restart. |
9 | Output Disabled | Indicates that the output is currently disabled because of the reference clock dying. The IP makes no further updates to the LPF. This bit only clears following an algorithm restart sequence. |
10 | diff_diff_value Output Overflow | This output value is smaller than the internal value you use. Indicates an overflow if the smaller value saturates. Consider increasing C_ERR_VAL_BITS. This bit only resets after an algorithm restart. |
11 | (diff_diff_value – last diff_diff_value) Output Overflow | This output value is smaller than the internal value. Indicates an overflow if the smaller value saturates. Consider increasing C_ERR_VAL_BITS. This bit only resets after a restart. |
Bits | Name | Description |
---|---|---|
15:8 | Reference Jitter Value
|
This value defines a genlock region equal to +/- number of pixels, where a SOF signal is allowed to jitter before the frame is outside the genlock region |
6:4 | GPO Clock Divider | This register defines the sample rate at which the IP updates the GPO with a new value.
|
0 | Reset Frame Counter | Reset the frame counter register. |
Bits | Name | Description |
---|---|---|
31:16 | GPO Error Region 2
|
This value defines the upper bound for the first GPO error mapping region. This value also defines the lower bound for the second GPO error mapping region. |
15:0 | GPO Error Region 1 | This value defines the lower bound for the first GPO error mapping region. This value defines the upper bound for the GPO genlock mapping region. |
Bits | Name | Description |
---|---|---|
31:16 | GPO Error Region 4 |
This value defines the upper bound for the third GPO error mapping region. This value defines the lower bound for the fourth GPO error mapping region. |
15:0 | GPO Error Region 3 | This value defines the lower bound for the third GPO error mapping region. This value defines the upper bound for the second GPO error mapping region |
Bits | Name | Description |
---|---|---|
31:0 | Total Pixels per Frame | Count of number of pixels per input frame |
Bits | Name | Description |
---|---|---|
31:16 | SOF Delay |
Count of number of pixels between receive and transmit SOF signals |
15:0 | Jitter Counter | Count of number of pixels between two consecutives SOF pulses |
Bits | Name | Description |
---|---|---|
31:0 | Bad Frames Counter | Count of frames that are outside the predefined genlock region set using the Reference Jitter Value |
Bits | Name | Description |
---|---|---|
0 | Enable |
You can enable the LPF anytime if the PFD is not enabled as no input values enter the LPF. |
1 | Integral Accumulator Reset Disable | If the DAC output reaches its maximum value (in either positive or negative direction), it automatically resets the Integral to the reset value as defined in LPF Control 2 register. Writing 1 to this bit stops the automatic reset, which may be useful for debugging. |
2 | Lock Loss Confidence Count Enable | This bit turns on the confidence counter for detection loss of lock. The IP gains lock when the lock confidence counter reaches its maximum value (C_LOCK_CNT_SIZE) and the IP sees successive no errors. However, a single error causes loss of lock immediately. Enabling this bit allows you to use the same confidence counter for indicating loss of lock. The IP indicates only if it reaches its minimum value of zero loss of. Hence lock status changes only when the extremes of the confidence counter are hit. |
7:3 | Lock Status LSB Position | By default, the IP allows 1 LSB bit change that does not change the lock status. You can increase the number of LSB bits by up to 31 (to 32 LSB) using these register bits. If the LSB position exceeds the size of the error value (C_CLK_DIV_BITS for diff_val in Phase mode, or C_ERR_VAL_BITS for diff_diff_val in Frequency mode), no amount of error causes the IP to lose lock. |
17:16 | Locked Status Control | Controls how the IP derives the Locked Status in the LPF Status Register. 00 = Frequency mode. Diff_Diff_Val Input is very small. The IP allows 1 LSB change and still indicates lock. You can increase the LSB position by up to a further 3 positions (to 4) using bits 31:30. Increase when you see larger error values because of larger sampling windows or jittery input. 01 = Phase mode. Diff_Val Input is very small. The IP allows 1 LSB change and still indicates lock. You can increase the LSB position by up to a further 3 positions (to 4) using bits 31:30.
|
18 | I Mode | Defines the integral mode.
|
19 | P Mode | Defines the proportional mode
|
24 | D Mode | Defines the differential mode.
|
25 | Negative I Gain | Inverts the sign of the 2’s complement input error. A positive input turns negative and vise-versa for the integral gain. Select this value after selecting I Mode. |
26 | Negative P Gain | Inverts the sign of the 2’s complement input error A positive input turns negative and vise-versa for the proportional gain. Select this value after selecting P Mode. |
27 | Negative D Gain | Inverts the sign of the 2’s complement input error. A positive input turns negative and vise-versa for the differential gain. Select this value after selecting D Mode. |
28 | I Gain Fraction | This bit reverses the direction of the I Gain powers of 2 shift, producing fractions of gain, instead of whole number gain. |
29 | Reset DAC Saturation Status | Setting high clears any latched DAC Saturation status as indicated in the LPF Status register. You must return this bit low. |
Bits | Name | Description |
---|---|---|
31:0 | Integral Accumulator Reset Value | Value the IP loads into the 32 LSBs of the integral accumulator at reset or if it is reset by saturation (if on). If the internal integral size is greater than 31 bits, the IP uses the MSB of this register as a sign extend. |
Bits | Name | Description |
---|---|---|
0 | Locked | Indicates when the error from the PFD reduces to a very small amount indicating locked status. |
1 | Integral Overflow | Indicates that an overflow in the integral accumulator is occurring and is reaching its maximum positive or negative value. It remains at that value until reset as part of a restart (refer to Software Usage). This bit indicates a serious error and the VCXO can be tracking anywhere. |
2 | DAC Saturated | Indicates that the DAC value output from the filter reaches its maximum positive or negative value. It automatically resets the Integral accumulator to its reset value unless you disable it using the LPF Control 1 register bit 1. This bit remains set until you clear it using bit 29 in the LPF Control 1 register. |
Bits | Name | Description |
---|---|---|
0 | Output Enable | ‘0’ Outputs High Impedance on the VCXO Driver Pin. ‘1’ enables the DAC to drive the pin. Avoid contention before enabling the DAC and any HW I2C writes in advance. |
3:1 | DAC Output Data Select | Controls the PWM output via binary offset input value:
|
4 | Hold | Hold value and do not update anymore. Only valid for DAC Output Data Select = 001. |
5 | Output Force Low | When set, the IP forces the PWM output low and ignores the output mode. Output Force High has a higher priority. |
6 | Output Force High | When set, the IP forces the PWM output high and ignores the output mode. This bit takes priority over Output Force Low. |
7 | Output Clock Divide Disable | By default, the IP sets the output clock rate of the DAC control pin using the build time parameter C_DAC_CLK_DIV. If this bit is 1, the build time divide is disabled, and the output clock rate runs at full speed (which is half the VCXO frequency). |
31:8 | CPU DAC Output Data Value | Only available if DAC Output Data Select = 100. Value must be offset binary range to the size of the DAC output as in the DAC Status Register. 2’s complement to offset binary conversion is invert MSB. Examples (assuming 24bit DAC size):
|
Bits | Name | Description |
---|---|---|
23:0 | Current DAC Output Data Value | Current offset binary range number that the DAC produces. |
Bits | Name | Description |
---|---|---|
7:0 | I Gain | Integral Gain. Provides powers of 2 shifts to the input error value e(t) (2’s complement positive or negative number). The IP adds or subtracts this value into the Integrator before adding it to the final output sum. Valid values are 0 to 15 where 0 means that the IP does not use the integral in the control value to the DAC. Example: Gain set to 7, gives 2^(7-1) = 64 i.e. the input e(t) is multiplied by 64. The input error value the IP uses depends on the I Mode bit and is either Diff_Val for Phase Mode or Diff_Diff_Val for Frequency Mode. You can invert the gain such that in the example above the input can be multiplied by -64. You invert the gain with the Negative I Gain Mode bit. Modes may not be available because of build parameters even though the bits remain persistent in this control register. Identify build time parameters using the LPF Status register. |
15:8 | P Gain | Proportional gain. Provides powers of 2 shifts to the input error value e(t) (2’s complement positive or negative number). The IP adds or subtracts this value to the final output sum. Valid values 0 to 15 where 0 means that IP does not use the in the control value to the DAC. Example: Gain set to 7, gives 2^(7-1) = 64 i.e. the input e(t) is multiplied by 64. The Input Error Value depends on the P Mode bit and is either Diff_Val for Phase Mode or Diff_Diff_Val for Frequency Mode. You can invert the gain such that in the example above the input can be multiplied by -64. Set the gain using the Negative P Gain Mode bit. Additionally, changes the gain shift (left or right) using the I Gain Fraction bit. Right Shifts produce fractional power of 2, which are useful after locking to reduce jitter caused by changes in the input error. Modes may not be available because of build parameters even though the bits remain persistent in this control register. Use the LPF Status register to identify build time parameters. |
23:16 | D Gain | Derivative gain. Provides powers of 2 shifts to the input error value e(t) (2’s complement positive or negative number). The IP adds or subtracts this value to the final output sum. Valid values 0 to 15 where 0 means that the derivative is not used in the control value to the DAC. Example: Gain set to 7, gives 2^(7-1) = 64 i.e. the input e(t) is multiplied by 64. The input error value depends on the D Mode bit and is either Diff_Diff_Val for Phase Mode or (Diff_Diff_Val – last Diff_Diff_Val) for Frequency Mode. You can invert the gain such that in the example above the input can be multiplied by -64. Set this gain using the Negative D Gain Mode bit. Modes may not be available because of build parameters even though the bits remain persistent in this control register. Use the LPF Status register to identify build time parameters. |
Bits | Name | Description |
---|---|---|
31:0 | VCXO Clock Measure | Count of clock ticks over 1 second. Zero indicates clock not running. Spurious counts indicate unstable clock. Stable clocks may deviate by a couple of counts because of frequency of CPU clock used to measure against and metastability. |
Bits | Name | Description |
---|---|---|
31:0 | Ref 0-3 Clock Measure | Count of clock ticks over 1 second. Zero indicates clock not running. Spurious counts could indicate unstable clock. Stable clocks may deviate by a couple of counts because of frequency of CPU clock the IP uses to measure against and metastability. |
Bits | Name | Description |
---|---|---|
31:0 | Current e(t) | This value indicates the current internal e(t) value (PFD counter difference value Diff_Val) that represents the continuous error difference value. It is a 2’s complement value representing positive and negative numbers indicating which counter (reference clock or VCXO clock) is ahead. For Frequency Mode, the error value should trend to a value and remain there. Although it may oscillate around the trend value and drift slowly over time. For Phase Mode, the error value should reduce to zero and remain there. Although it may oscillate +/- 1. It should not drift over time. |
Bits | Name | Description |
---|---|---|
26:22 | VCXO Integer number part | Sets the integer part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to 8. |
21:0 | VCXO Fractional number part | Sets the fractional part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to (2^22) * (0.750). The 2^22 multiplying factor is because of this IP using 22 bits to represent the fractional part in a fixed-point format. |
Bits | Name | Description |
---|---|---|
26:22 | Ref 0-3 Integer number part | Sets the integer part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to 8. |
21:0 | Ref 0-3 Fractional number part | Sets the fractional part of the clock ratio value. For example, if the clock ratio value is 8.750, this field needs to be set to (2^22) * (0.750). The 2^22 multiplying factor is because of this IP using 22 bits to represent the fractional part in a fixed-point format. |