36.1. About the Video Frame Buffer IP
The frame buffer supports:
- Triple or double buffering for progressive video frames
- Double buffering for interlaced video fields
- Auxiliary control packets. Local storage for up to 255. The IP can optionally drop and repeat auxiliary packets with their associated frame.
- Maximum frame resolutions of 16384 by 16384 pixels with 1 to 8 pixels in parallel and any color space
- Configurable memory packing scheme
- Optional dropping of broken frames
- Frame statistics counters
The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The Video Frame Buffer IP takes input resolution information from image information packets or extracts it using the register interface for lite variants.
An Avalon memory-mapped interface allows you to read frame statistics and turn the frame buffer output off and on at run time. You must have this interface for lite variants.
For details about latency and reset behavior for the Video Frame Buffer, refer to Video and Vision IPs Functional Description.