Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 6/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

18.1. About the Deinterlacer IP

The IP takes a stream of interlaced video fields and outputs progressive frames generated using a bob or weave algorithm. The IP passes progressive video frames through unchanged.

The bob algorithm duplicates each line of a video such that the IP produces two lines of data for each one line of incoming data. The deinterlacing algorithm can be setup for:

  • Deinterlacing F0 fields while dropping F1 fields
  • Deinterlacing F1 fields while dropping F0 fields
  • Deinterlacing both F0 and F1 fields

For the bob deinterlacer, with a regular input sequence of alternating field types, the frame rate on the output matches the input field rate when deinterlacing both F0 and F1 fields. Otherwise the IP halves the field rate.

The weave algorithm creates an output frame by filling all the missing lines in the current field with lines from the previous field. With a regular input sequence of alternating field types, the IP halves the field rate.

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. For full variants, the deinterlacer IP decodes input resolutions and field type by reading image information packets. Lite variants use the register interface to determine input resolutions and whether the video is progressive or interlaced. Lite variants then decode the axi4s_vid_in_tuser[1] signal to determine the incoming field's interlaced type. If you require weave or motion adaptive deinterlacing, use protocol converters and the video and image processing suite deinterlacer II IP.