Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 6/26/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

34.2. Test Pattern Generator IP Parameters

The IP offers run time and compile time parameters.
Parameter Value Description
Interface Configuration
Lite mode On or off Turn on to use the Lite variant of the Intel FPGA Streaming Video protocol.
Bits per color sample 8 to 16 Select the number of bits per color sample
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel at the output interface.
Output format 4:4:4, 4:2:2, 4:2:0. Variable or Monochrome Select the chroma sampling format for the output interface.
General
Memory-mapped control interface On or off Turn on for the Avalon memory-mapped control agent interface and allow runtime configuration via the register map. You must have the Avalon memory-mapped control agent interface when you turn on Lite mode.
Separate clock for control interface On or off Turn on for a separate clock for the control agent interface.
Debug features On or off Turn on for read back of writeable registers via the control agent interface.
Pipeline ready signals On or off Turn on to add extra pipeline registers to the AXI4-S tready signals.
Shared configuration
Fixed interlacing 0 to 15 Only if Memory-mapped control interface is not on. Select if output stream is progressive, interlaced with F0 sent first after reset, or interlaced with F1 sent first after reset. If Lite mode is off, the selected value populates the interlaced identifier field in the output image info packets.
  1. Values 0-7 give progressive output
  2. Values 8-11 give interlaced output with F0 send first
  3. Values 12-15 give interlaced output with F1 sent first
.
Fixed frame width 1 to 16384 Only if Memory-mapped control interface is off. Select the width of the frames and fields produced at the output. If the selected output subsampling is 4:2:2 or 4:2:0, the frame width must be a multiple of 2.
Fixed frame height 1 to 16384 Only if Memory-mapped control interface is off. Select the height of the frames produced at the output. If interlaced output is on, the height of each field is half this value. If the selected output subsampling is 4:2:0, the frame height must be a multiple of 2.
Pattern configuration
Fixed bars mode Color, Greyscale, Black and white, Mixed Only if Memory-mapped control interface is off and you select bars test pattern. Sets which variant of the bars pattern to use.
Fixed R/Cr 0 – (2^ Bits per color sample)-1 Only if Memory-mapped control interface is off and you select constant color test pattern. Sets the value the IP uses for the R color plane if the output is RGB, or the Cr color plane if the output is YCbCr.
Fixed G/Y 0 – (2^ Bits per color sample)-1 Only if Memory-mapped control interface is off and you select the constant color test pattern. Sets the value the IP uses for the G color plane if the output is RGB, or the Y color plane if the output is YCbCr.
Fixed B/Cb 0 – (2^ Bits per color sample)-1 Only if Memory-mapped control interface is off and you select the constant color test pattern. Sets the value the IP uses for the B color plane if the output is RGB, or the Cb color plane if the output is YCbCr.
Number of test patterns 1 to 8 Set the number of test pattern configurations to turn on.

Core 0 test pattern

Core 1 test pattern

Core 2 test pattern

Core 3 test pattern

Core 4 test pattern

Core 5 test pattern

Core 6 test pattern

Core 7 test pattern

Bars, Constant color, SDI pathological Selects the test pattern for each configuration.

Core 0 color space

Core 1 color space

Core 2 color space

Core 3 color space

Core 4 color space

Core 5 color space

Core 6 color space

Core 7 color space

RGB, YCbCr 444, YCbCr 422, YCbCr 420, MONO Sets the output color space and chroma sampling for each test pattern configuration.