37.1. About the Video Frame Reader IP
The frame reader supports:
- Maximum frame resolutions of 16,384 by 16,384 pixels with 1 to 8 pixels in parallel and any color space
- Reading of progressive frames or interlaced fields
- Configurable memory packing scheme
- Runtime configurable frame location in memory
- Configurable number of buffer sets
- Continuous,single-shot, and frame sync modes over a single buffer set or multiple buffer sets
- Configurable interrupt on read completion
The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The Video Frame Reader IP takes resolution information from the configurable buffer set registers.
An Avalon memory-mapped interface allows you to configure buffer sets and change the operating mode at run time. You must have this interface for both full and lite variants.
For details about latency and reset behavior for the Video Frame Reader, refer to Video and Vision IPs Functional Description.