15.3. Clocked Video to Full-Raster Converter Block Description
The clocked video bus can contain additional sideband signals, such as discrete 16-bit signals for the width and height of the raster. The IP ignores these sideband signals and copies some signals CPU registers. The sideband signals provide backward IO interface compatibility between the IP and legacy Intel clocked video input and clocked video output interfaces.
The AXI4-S tUser signal cannot be generated automatically from the clocked video timing signals. The tUser is asserted for true pixels (0,0) in the full video raster, but the location of (0,0) relative to the timing strobes varies by video standard. Therefore, you need either a CPU interface to instruct the tUser logic where to place in the raster the tUser, or the IP is restricted to a single video standard.