40.3. Video Timing Generator IP Functional Description
This processor decoder and register map provide a simple interface to the processor bus. The IP shows all run-time parameters for the video timing through the register map. All run-time parameters default to values provided at build-time.
These counters and logic contain a horizontal pixel counter and vertical line counter. The submodule produces the video timing signals f, v, and h as specified by the processor registers. The processor specifies additional programmable “pulses” to aid other modules in the system. For example, a programmable pulse can trigger the preload on the SDRAM controller.
This formatter takes the f, v, and h signals and forms a full-raster bus, or an Intel clocked video bus. You select the type of bus at build time.
The output timing bus contains space for pixel data. The value of the pixel data can be set by the processor at run time but initially defaults to the value defined at build time.
The IP has a build-time option to include or exclude the tReady signal for the full-raster interface. However, the IP does not use this signal. The IP includes it only to allow connection to a full-raster bus that includes this signal. If the tReady signal is deasserted, the Video Timing Generator IP continues to produce data.
The Timing Generator produces output on the transmit clock for the connectivity IP.
The processor interface operates on the processor clock domain. Drive the processor interface from a known stable clock, such as a dedicated processor clock. Do not drive connectivity IP from the transmit clock as it can be unstable. For example when standards change, which can potentially corrupt the processor interface.