Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 6/26/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

25.1. About the Genlock Signal Router IP

The IP is a multichannel genlock strobe extractor and router. This IP passes genlock timing signals to internal or external FPGA multirate video clock generators. The IP helps video input and output clock genlock and frame synchronization, based on video timing markers derived from video connectivity IPs.
Figure 60. Genlock Signal Router IP Block Diagram

Data is input to and output from the Genlock Signal Router IP via a selectable number of ports. The final number of input and output ports is in the range 1 to 32 inclusive, which you can configure in the Genlock Signal Router IP GUI.

At build time, you can configure the input port interfaces in three different modes: Intel video streaming full-raster, Intel clocked video, and clock only mode. The IP automatically extracts timing information from the input signals, and then routes the signals between the input and output ports. You can control the input-to-output routing dynamically at run-time using the processor interface.

The output interface for this IP provides two optional interfaces:

  • An interface with a set of discrete timing signals, such as field flag, horizontal, and vertical synchronization timing markers.
  • An interface that provides clocks only ports

The timing markers can then pass to internal or external FPGA multirate video clock generators.