DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023

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Document Table of Contents VIDEO_MODE_CONTROL (0x54)

Table 139.  VIDEO_MODE_CONTROL (0x54)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Interlaced 0 RW

Set to 1 for interlaced video.

Set to 0 for progressive video.