DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback STATUS (0x50)

Table 136.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Status 0 RO When asserted, the AXI2CV is producing data. 0x0