DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2. About This IP

This document describes the DisplayPort Intel® FPGA IP, which provides support for next-generation video display interface technology. The Video Electronics Standards Association (VESA) defines the DisplayPort standard as an open digital communications interface for use in internal connections such as:

  • Interfaces within a PC or monitor
  • External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display

The DisplayPort Intel® FPGA IP supports scalable Main Link with 1, 2, or 4 lanes, with 5 selectable data rates on each lane: 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps, 10.0 Gbps, and 20.0 Gbps.

Figure 1. DisplayPort Source and Sink Communication in DP2.0

There are two different data paths within DP2.0. It is on 128B/132B Channel Coding when running at 10.0 Gbps and above. It falls back to 8B/10B Channel Coding when it is at 8.1 Gbps or below. DP1.4 only supports up to 8.1 Gbps on 8B/10B Channel Coding.

Main Link transports video and audio streams with embedded clocking to decoupled pixel and audio clocks from the transmission clock. The IP transmits Main Link's data in scrambled ANSI 8B/10B format in DP1.4 or 128B/132B in DP2.0 and includes redundancy in the data transmission for error detection. For secondary data, such as audio, the IP uses Solomon Reed coding for error detection.

The DisplayPort's AUX channel consists of an AC-coupled terminated differential pair. AUX channel uses Manchester II coding for its channel coding and provides a data rate of 1 Mbps. Each transaction takes less than 500 µs with a maximum burst data size of 16 bytes.

Figure 2. DisplayPort Source and Sink Communication