DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

11.6.16. DPRX0_VBID

VB-ID register, DPRX0_VBID.

Address: 0x002f

Direction: RO

Reset: 0x00000000

Table 184.  DPRX0_VBID Bits

Bit

Bit Name

Function

31:8

Unused

9 Link_Timing_Lock

8B/10B Channel Coding:

Reserved

128B/132B Channel Coding:

0 = Link Timing upon LLCP, unlocked

1 = Link Timing upon LLCP, locked

8 Unused  

7

MSA_LOCK

0 = MSA unlocked

1 = MSA locked (on all lanes)

6

VBID_LOCK

0 = VB-ID unlocked

1 = VB-ID locked (on all lanes)

5:0

VBID

VB-ID flags (refer to the VESA DisplayPort Standard).