DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
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10.2.6. DPTX0_MSA_HSW

Address: 0x0025

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 70.  DPTX0_MSA_HSW Bits

Bit

Bit Name

Function

31:15

Unused

14:0

HSW

Main stream attribute horizontal sync width