DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.7.1. DPTX_MST_VCPTAB0

VC Payload ID Table

Address: 0x00a2

Direction: RW

Reset: 0x00000000

Table 101.  DPTX_MST_VCPTAB0 Bits
Bit Bit Name Function
31:28 VCPSLOT7 VC payload ID for slot 7
27:24 VCPSLOT6 VC payload ID for slot 6
23:20 VCPSLOT5 VC payload ID for slot 5
19:16 VCPSLOT4 VC payload ID for slot 4
15:12 VCPSLOT3 VC payload ID for slot 3
11:8 VCPSLOT2 VC payload ID for slot 2
7:4 VCPSLOT1 VC payload ID for slot 1
3:0 VCPSLOT0

8B/10B Coding Channel:

Reserved

128B/132B Channel Coding:

VC Payload ID for slot 0