DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

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6.7. Sink Clock Tree

The IP receives DisplayPort serial data across the high-speed serial interface (HSSI). Refer to the Transceiver Reconfiguration for Different Design Variants table in the Transceiver Reconfiguration Interface section for the HSSI reference clock requirements. You can supply this frequency to the HSSI using a reference clock provided by an Intel FPGA PLL or pins.

The IP synchronizes HSSI 20-, 40-, or 32-bit data to a single HSSI[0] clock that clocks the data into the DisplayPort front-end decoder.

  • If you select dual symbol mode in DP1.4, this clock is equal to the link rate divided by 20 (270, 135, or 81 MHz).
  • If you turn on quad symbol mode in DP1.4, this clock is equal to the link rate divided by 40 (202.5, 135, 67.5, or 40.5 MHz).
  • If you select DP2.0 UHBR10 link rate, this clock is equal to the link rate divided by 32 (312.5 MHz).
The IP crosses the reconstructed pixel data into a local video clock (rxN_vid_clk) through an output DCFIFO, which drives the pixel stream output. The rxN_vid_clk frequency must be higher than or equal to the video clock in the up-stream source.
  • If rxN_vid_clk is slower than the up-stream video clock, the DCFIFO overflows.
  • If the rxN_vid_clk is faster than the up-stream source video clock, the output port experiences a deassertion of the valid port on cycles in which pixel data is not available.

The optimum frequency is the exact clock rate in the up-stream source. You require pixel clock recovery techniques to determine this clock frequency.

Secondary stream data is clocked by rx_ss_clk. The sink IP also requires a 16-MHz clock (aux_clk) to drive the internal AUX controller and an Avalon clock for the Avalon® memory-mapped interface (clk).

Figure 45. Sink Clock Tree