DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

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6.6.3.2. Video Stream Out Interface

This interface provides access to the post-scrambler DisplayPort data, which is useful for low-level debugging source equipment. The 8-bit symbols received are organized as shown in the following table, where n increases with time (at each main link clock cycle, by 2 for dual-symbol mode or by 4 for quad-symbol mode).

Table 52.  rxN_stream_data Bit Allocation
Bit Dual-Symbol Mode Quad-Symbol Mode

127:120

Not applicable

Lane 3 symbol n + 3

119:112

Not applicable

Lane 3 symbol n + 2

111:104

Not applicable

Lane 3 symbol n + 1

103:96

Not applicable

Lane 3 symbol n

95:88

Not applicable

Lane 2 symbol n + 3

87:80

Not applicable

Lane 2 symbol n + 2

79:72

Not applicable

Lane 2 symbol n + 1

71:64

Not applicable

Lane 2 symbol n

63:56

Lane 3 symbol n + 1

Lane 1 symbol n + 3

55:48

Lane 3 symbol n

Lane 1 symbol n + 2

47:40

Lane 2 symbol n + 1

Lane 1 symbol n + 1

39:32

Lane 2 symbol n

Lane 1 symbol n

31:24

Lane 1 symbol n + 1

Lane 0 symbol n + 3

23:16

Lane 1 symbol n

Lane 0 symbol n + 2

15:8

Lane 0 symbol n + 1

Lane 0 symbol n + 1

7:0

Lane 0 symbol n

Lane 0 symbol n

  

When data is received, data is produced on lane 0, lanes 0 and 1, or on all four lanes according to how many lanes are currently used and link trained on the main link. The IP provides the data output immediately after the data passes through the descrambler and features all control symbols, data, and original timing. As data is always valid at each and every clock cycle, the rxN_stream_valid signal remains asserted.