DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.4. FEC Registers

These registers are used to control access to FEC Error registers and read FEC Error Counters. All registers are applicable to 128B/132B Channel Coding only. When IP is operating in 8B/10B Channel Coding, all registers are Reserved.