DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/18/2023
Public

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11.4.2. DPRX_FEC_ERROR_COUNT

FEC Error Counter Register

Address: 0x000A

Direction: RO

Reset: 0x00000000

Table 167.  DPR_FEC_ERROR_COUNT Bits

Bit

Bit Name

Function

31:16

Unused

Symbol error counter for lane 3

15 FEC_ERROR_COUNT_VALID
  • 0 = Not valid
  • 1 = Valid
14:0 FEC_ERROR_COUNT

FEC Error Count.

Value selected by FEC_ERR_COUNT_SEL and FEC_LANE_DEC_SEL.

Cleared when FEC_ERR_COUNT_SEL set to 000.

These registers are meant for internal use and are not exposed in the DPCD.