DisplayPort Intel® FPGA IP User Guide

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ID 683273
Date 4/18/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Quick Reference 2. About This IP 3. Getting Started 4. DisplayPort Intel® FPGA IP Hardware Design Examples 5. DisplayPort Source 6. DisplayPort Sink 7. DisplayPort Intel® FPGA IP Parameters 8. DisplayPort Intel® FPGA IP Simulation Example 9. DisplayPort API Reference 10. DisplayPort Source Register Map and DPCD Locations 11. DisplayPort Sink Register Map and DPCD Locations 12. DisplayPort Intel® FPGA IP User Guide Archives 13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide
1. DisplayPort Intel® FPGA IP Quick Reference x
1.1. DisplayPort Terms and Acronyms
2. About This IP x
2.1. Release Information 2.2. Device Family Support 2.3. IP Core Verification 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options 3.3. Simulating the Design 3.4. Compiling the Full Design and Programming the FPGA 3.5. Calculating Video Bandwidth and Recovered Pixel Clock Frequency
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.3. Simulating the Design x
3.3.1. Simulating with the ModelSim Simulator
4. DisplayPort Intel® FPGA IP Hardware Design Examples x
4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ 7 F-Tile Devices 4.2. HDCP Over DisplayPort Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices
4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices x
4.3.1. Clock Recovery Core 4.3.2. Transceiver and Clocking 4.3.3. Required Hardware 4.3.4. Design Walkthrough 4.3.5. DisplayPort Link Training Flow 4.3.6. DisplayPort Post Link Training Adjust Request Flow (LQA) 4.3.7. Translating DisplayPort Link Training AUX Transactions 4.3.8. DisplayPort MST Source User Application
4.3.1. Clock Recovery Core x
4.3.1.1. Clock Recovery Core Parameters 4.3.1.2. Clock Recovery Interface
4.3.1.2. Clock Recovery Interface x
4.3.1.2.1. Video Input Port
4.3.4. Design Walkthrough x
4.3.4.1. Set Up the Hardware 4.3.4.2. Copy the Design Files to Your Working Directory 4.3.4.3. Build the FPGA Design 4.3.4.4. Load and Run the Software 4.3.4.5. View the Results
5. DisplayPort Source x
5.1. IP to Transceiver Parallel Data Interface Width 5.2. Main Data Path 5.3. Controller Interface 5.4. Sideband Channel 5.5. Source Embedded DisplayPort (eDP) Support 5.6. HDCP 1.3 TX Architecture 5.7. HDCP 2.3 TX Architecture 5.8. Source Interfaces 5.9. Source Clock Tree
5.2. Main Data Path x
5.2.1. Video Packetizer Path 5.2.2. Video Geometry Measurement Path 5.2.3. Audio and Secondary Stream Encoder Path 5.2.4. Training and Link Quality Patterns Generator
5.2.4. Training and Link Quality Patterns Generator x
5.2.4.1. DP1.4 (8B/10B Channel Coding) 5.2.4.2. DP2.0 (128B/132B Channel Coding)
5.8. Source Interfaces x
5.8.1. Controller Interface 5.8.2. AUX Interface 5.8.3. Video Interface 5.8.4. TX Transceiver Interface 5.8.5. Transceiver Reconfiguration Interface 5.8.6. Transceiver Analog Reconfiguration Interface 5.8.7. Secondary Stream Interface 5.8.8. Audio Interface
5.8.3. Video Interface x
5.8.3.1. Video Interface (TX Video IM Enable = 0) 5.8.3.2. Video Interface (TX Video IM Enable = 1) 5.8.3.3. Video Interface (Enable Active Video Data Protocols = AXIS-VVP Full)
6. DisplayPort Sink x
6.1. Transceiver to IP Parallel Data Interface Width 6.2. Sink Embedded DisplayPort (eDP) Support 6.3. Sink Non-GPU Mode Support 6.4. HDCP 1.3 RX Architecture 6.5. HDCP 2.3 RX Architecture 6.6. Sink Interfaces 6.7. Sink Clock Tree
6.6. Sink Interfaces x
6.6.1. Controller Interface 6.6.2. AUX Interface 6.6.3. Debugging Interface 6.6.4. Video Interface 6.6.5. Video Interface (Enable Active Video Data Protocols = AXIS-VVP Full) 6.6.6. Clocked Video Input Interface 6.6.7. RX Transceiver Interface 6.6.8. Transceiver Reconfiguration Interface 6.6.9. Secondary Stream Interface 6.6.10. Audio Interface 6.6.11. Non-GPU Mode EDID Interface 6.6.12. MSA Interface
6.6.2. AUX Interface x
6.6.2.1. AUX Debug Interface 6.6.2.2. EDID Interface
6.6.3. Debugging Interface x
6.6.3.1. Link Parameters Interface 6.6.3.2. Video Stream Out Interface
7. DisplayPort Intel® FPGA IP Parameters x
7.1. DisplayPort Intel® FPGA IP Source Parameters 7.2. DisplayPort Intel® FPGA IP Sink Parameters
8. DisplayPort Intel® FPGA IP Simulation Example x
8.1. Design Walkthrough
8.1. Design Walkthrough x
8.1.1. Copy the Simulation Files to Your Working Directory 8.1.2. Generate the IP Simulation Files and Scripts, and Compile and Simulate 8.1.3. View the Results
9. DisplayPort API Reference x
9.1. Using the Library 9.2. btc_dprx_syslib API Reference 9.3. btc_dprx_aux_get_request 9.4. btc_dprx_aux_handler 9.5. btc_dprx_aux_post_reply 9.6. btc_dprx_baseaddr 9.7. btc_dprx_dpcd_gpu_access 9.8. btc_dprx_edid_set 9.9. btc_dprx_hpd_get 9.10. btc_dprx_hpd_pulse 9.11. btc_dprx_hpd_set 9.12. btc_dprx_lt_eyeq_init 9.13. btc_dprx_lt_force 9.14. btc_dprx_rtl_ver 9.15. btc_dprx_sw_ver 9.16. btc_dprx_syslib_add_rx 9.17. btc_dprx_syslib_info 9.18. btc_dprx_syslib_init 9.19. btc_dprx_syslib_monitor 9.20. btc_dprx_mst_link_addr_rep_set 9.21. btc_dprx_mst_conn_stat_notify_req 9.22. btc_dprx_mst_conn_stat_notify_rep 9.23. btc_dptx_syslib API Reference 9.24. btc_dptx_aux_i2c_read 9.25. btc_dptx_aux_i2c_write 9.26. btc_dptx_aux_read 9.27. btc_dptx_aux_write 9.28. btc_dptx_baseaddr 9.29. btc_dptx_edid_block_read 9.30. btc_dptx_edid_read 9.31. btc_dptx_fast_link_training 9.32. btc_dptx_hpd_change 9.33. btc_dptx_is_link_up 9.34. btc_dptx_link_bw 9.35. btc_dptx_link_training 9.36. btc_dptx_rtl_ver 9.37. btc_dptx_set_color_space 9.38. btc_dptx_sw_ver 9.39. btc_dptx_syslib_add_tx 9.40. btc_dptx_syslib_init 9.41. btc_dptx_syslib_monitor 9.42. btc_dptx_test_autom 9.43. btc_dptx_video_enable 9.44. btc_dptx_mst_allocate_payload_rep 9.45. btc_dptx_mst_allocate_payload_req 9.46. btc_dptx_mst_clear_payload_table_rep 9.47. btc_dptx_mst_clear_payload_table_req 9.48. btc_dptx_mst_conn_stat_notify_req 9.49. btc_dptx_mst_down_rep_irq 9.50. btc_dptx_mst_enable 9.51. btc_dptx_mst_enum_path_rep 9.52. btc_dptx_mst_enum_path_req 9.53. btc_dptx_mst_get_msg_transact_ver_rep 9.54. btc_dptx_mst_get_msg_transact_ver_req 9.55. btc_dptx_mst_link_address_rep 9.56. btc_dptx_mst_link_address_req 9.57. btc_dptx_mst_remote_dpcd_wr_rep 9.58. btc_dptx_mst_remote_dpcd_wr_req 9.59. btc_dptx_mst_remote_i2c_rd_rep 9.60. btc_dptx_mst_remote_i2c_rd_req 9.61. btc_dptx_mst_set_color_space 9.62. btc_dptx_mst_tavgts_set 9.63. btc_dptx_mst_up_req_irq 9.64. btc_dptx_mst_vcpid_set 9.65. btc_dptx_mst_vcptab_addvc 9.66. btc_dptx_mst_vcptab_clear 9.67. btc_dptx_mst_vcptab_delvc 9.68. btc_dptx_mst_vcptab_update 9.69. btc_dptxll_syslib API Reference 9.70. btc_dptxll_hpd_change 9.71. btc_dptxll_hpd_irq 9.72. btc_dptxll_mst_cmp_ports 9.73. btc_dptxll_mst_edid_read_rep 9.74. btc_dptxll_mst_edid_read_req 9.75. btc_dptxll_mst_get_device_ports 9.76. btc_dptxll_mst_set_csn_callback 9.77. btc_dptxll_mst_topology_discover 9.78. btc_dptxll_stream_allocate_rep 9.79. btc_dptxll_stream_allocate_req 9.80. btc_dptxll_stream_calc_VCP_size 9.81. btc_dptxll_stream_delete_rep 9.82. btc_dptxll_stream_delete_req 9.83. btc_dptxll_stream_get 9.84. btc_dptxll_stream_set_color_space 9.85. btc_dptxll_stream_set_pixel_rate 9.86. btc_dptxll_sw_ver 9.87. btc_dptxll_syslib_add_tx 9.88. btc_dptxll_syslib_init 9.89. btc_dptxll_syslib_monitor 9.90. btc_dpxx_syslib Additional Types 9.91. btc_dprx_syslib Supported DPCD Locations
10. DisplayPort Source Register Map and DPCD Locations x
10.1. Source General Registers 10.2. Source MSA Registers 10.3. Source Link PHY Control and Status 10.4. Source Timestamp 10.5. Source CRC Registers 10.6. Source Audio Registers 10.7. Source MST Registers 10.8. Source AUX Controller Interface 10.9. Source-Supported DPCD Locations 10.10. Source AXI2CV Registers
10.1. Source General Registers x
10.1.1. DPTX_TX_CONTROL 10.1.2. DPTX_TX_STATUS 10.1.3. DPTX_TX_VERSION
10.2. Source MSA Registers x
10.2.1. DPTX0_MSA_MVID 10.2.2. DPTX0_MSA_NVID 10.2.3. DPTX0_MSA_HTOTAL 10.2.4. DPTX0_MSA_VTOTAL 10.2.5. DPTX0_MSA_HSP 10.2.6. DPTX0_MSA_HSW 10.2.7. DPTX0_MSA_HSTART 10.2.8. DPTX0_MSA_VSTART 10.2.9. DPTX0_MSA_VSP 10.2.10. DPTX0_MSA_VSW 10.2.11. DPTX0_MSA_HWIDTH 10.2.12. DPTX0_MSA_VHEIGHT 10.2.13. DPTX0_MSA_MISC0 10.2.14. DPTX0_MSA_MISC1 10.2.15. DPTX0_MSA_COLOR 10.2.16. DPTX0_VBID
10.3. Source Link PHY Control and Status x
10.3.1. DPTX_PRE_VOLT0/DPTX_REG_TXFFE0 10.3.2. DPTX_PRE_VOLT1/DPTX_REG_TXFFE1 10.3.3. DPTX_PRE_VOLT2/DPTX_REG_TXFFE2 10.3.4. DPTX_PRE_VOLT3/DPTX_REG_TXFFE3 10.3.5. DPTX_RECONFIG 10.3.6. DPTX_TEST_80BIT_PATTERN1/DPTX_TEST_264BIT_PATTERN1 10.3.7. DPTX_TEST_80BIT_PATTERN2/DPTX_TEST_264BIT_PATTERN2 10.3.8. DPTX_TEST_80BIT_PATTERN3/DPTX_TEST_264BIT_PATTERN3 10.3.9. DPTX_TEST_264BIT_PATTERN4 10.3.10. DPTX_TEST_264BIT_PATTERN5 10.3.11. DPTX_TEST_264BIT_PATTERN6 10.3.12. DPTX_TEST_264BIT_PATTERN7 10.3.13. DPTX_TEST_264BIT_PATTERN8 10.3.14. DPTX_TEST_264BIT_PATTERN9
10.7. Source MST Registers x
10.7.1. DPTX_MST_VCPTAB0 10.7.2. DPTX_MST_VCPTAB1 10.7.3. DPTX_MST_VCPTAB2 10.7.4. DPTX_MST_VCPTAB3 10.7.5. DPTX_MST_VCPTAB4 10.7.6. DPTX_MST_VCPTAB5 10.7.7. DPTX_MST_VCPTAB6 10.7.8. DPTX_MST_VCPTAB7 10.7.9. DPTX_MST_TAVG_TS 10.7.10. DPTX_MST_ECF0 10.7.11. DPTX_MST_ECF1
10.8. Source AUX Controller Interface x
10.8.1. DPTX_AUX_CONTROL 10.8.2. DPTX_AUX_COMMAND 10.8.3. DPTX_AUX_BYTE0 10.8.4. DPTX_AUX_BYTE1 10.8.5. DPTX_AUX_BYTE2 10.8.6. DPTX_AUX_BYTE3 10.8.7. DPTX_AUX_BYTE4 10.8.8. DPTX_AUX_BYTE5 10.8.9. DPTX_AUX_BYTE6 10.8.10. DPTX_AUX_BYTE7 10.8.11. DPTX_AUX_BYTE8 10.8.12. DPTX_AUX_BYTE9 10.8.13. DPTX_AUX_BYTE10 10.8.14. DPTX_AUX_BYTE11 10.8.15. DPTX_AUX_BYTE12 10.8.16. DPTX_AUX_BYTE13 10.8.17. DPTX_AUX_BYTE14 10.8.18. DPTX_AUX_BYTE15 10.8.19. DPTX_AUX_BYTE16 10.8.20. DPTX_AUX_BYTE17 10.8.21. DPTX_AUX_BYTE18 10.8.22. DPTX_AUX_RESET
10.10. Source AXI2CV Registers x
10.10.1. Source AXI2CV Registers Summary 10.10.2. Source AXI2CV Registers Description
10.10.2. Source AXI2CV Registers Description x
10.10.2.1. STATUS (0x50) 10.10.2.2. VIDEO_MODE_MATCH (0X51) 10.10.2.3. VIDEO_MODE_BANK_SELECT (0x53) 10.10.2.4. VIDEO_MODE_CONTROL (0x54) 10.10.2.5. VIDEO_MODE_SAMPLE_COUNT(0x55) 10.10.2.6. VIDEO_MODE_F0_LINE_COUNT (0x56) 10.10.2.7. VIDEO_MODE_F1_LINE_COUNT (0x57) 10.10.2.8. VIDEO_MODE_HORIZONTAL_FRONT_PORCH (0x58) 10.10.2.9. VIDEO_MODE_HORIZONTAL_SYNC_LENGTH (0x59) 10.10.2.10. VIDEO_MODE_HORIZONTAL_BLANKING (0x5A) 10.10.2.11. VIDEO_MODE_VERTICAL_FRONT_PORCH (0x5B) 10.10.2.12. VIDEO_MODE_VERTICAL_SYNC_LENGTH (0x5C) 10.10.2.13. VIDEO_MODE_VERTICAL_BLANKING (0x5D) 10.10.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E) 10.10.2.15. VIDEO_MODE_F0_VERTICAL_SYNC_LENGTH (0x5F) 10.10.2.16. VIDEO_MODE_F0_VERTICAL_BLANKING (0x60) 10.10.2.17. VIDEO_MODE_ACTIVE_PICTURE_LINE (0x61) 10.10.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62) 10.10.2.19. VIDEO_MODE_FIELD_RISING (0x63) 10.10.2.20. VIDEO_MODE_FIELD_FALLING (0x64) 10.10.2.21. VIDEO_MODE_VALID (0x6D)
11. DisplayPort Sink Register Map and DPCD Locations x
11.1. Sink General Registers 11.2. Sink Timestamp 11.3. Sink Bit-Error Counters 11.4. FEC Registers 11.5. 128B/132B Link Quality Test Pattern Registers 11.6. Sink MSA Registers 11.7. Sink Audio Registers 11.8. Sink MST Registers 11.9. Sink AUX Controller Interface 11.10. Sink CRC Registers 11.11. Sink-Supported DPCD Locations 11.12. Sink CV2AXI Registers
11.1. Sink General Registers x
11.1.1. DPRX_RX_CONTROL 11.1.2. DPRX_RX_STATUS 11.1.3. DPRX_BER_CONTROL 11.1.4. DPRX_BER_CNT0 11.1.5. DPRX_BER_CNT1
11.3. Sink Bit-Error Counters x
11.3.1. DPRX_BER_CNTI0 11.3.2. DPRX_BER_CNTI1
11.4. FEC Registers x
11.4.1. DPRX_FEC_CONFIG 11.4.2. DPRX_FEC_ERROR_COUNT
11.5. 128B/132B Link Quality Test Pattern Registers x
11.5.1. DPRX_BER_TEST_PATTERN
11.6. Sink MSA Registers x
11.6.1. DPRX0_MSA_MVID 11.6.2. DPRX0_MSA_NVID 11.6.3. DPRX0_MSA_HTOTAL 11.6.4. DPRX0_MSA_VTOTAL 11.6.5. DPRX0_MSA_HSP 11.6.6. DPRX0_MSA_HSW 11.6.7. DPRX0_MSA_HSTART 11.6.8. DPRX0_MSA_VSTART 11.6.9. DPRX0_MSA_VSP 11.6.10. DPRX0_MSA_VSW 11.6.11. DPRX0_MSA_HWIDTH 11.6.12. DPRX0_MSA_VHEIGHT 11.6.13. DPRX0_MSA_MISC0 11.6.14. DPRX0_MSA_MISC1 11.6.15. DPRX0_MSA_COLOR 11.6.16. DPRX0_VBID
11.7. Sink Audio Registers x
11.7.1. DPRX0_AUD_MAUD 11.7.2. DPRX0_AUD_NAUD 11.7.3. DPRX0_AUD_AIF0 11.7.4. DPRX0_AUD_AIF1 11.7.5. DPRX0_AUD_AIF2 11.7.6. DPRX0_AUD_AIF3 11.7.7. DPRX0_AUD_AIF4
11.8. Sink MST Registers x
11.8.1. DPRX_MST_VCPTAB0 11.8.2. DPRX_MST_VCPTAB1 11.8.3. DPRX_MST_VCPTAB2 11.8.4. DPRX_MST_VCPTAB3 11.8.5. DPRX_MST_VCPTAB4 11.8.6. DPRX_MST_VCPTAB5 11.8.7. DPRX_MST_VCPTAB6 11.8.8. DPRX_MST_VCPTAB7
11.9. Sink AUX Controller Interface x
11.9.1. DPRX_AUX_CONTROL 11.9.2. DPRX_AUX_STATUS 11.9.3. DPRX_AUX_COMMAND 11.9.4. DPRX_AUX_BYTE0 11.9.5. DPRX_AUX_BYTE1 11.9.6. DPRX_AUX_BYTE2 11.9.7. DPRX_AUX_BYTE3 11.9.8. DPRX_AUX_BYTE4 11.9.9. DPRX_AUX_BYTE5 11.9.10. DPRX_AUX_BYTE6 11.9.11. DPRX_AUX_BYTE7 11.9.12. DPRX_AUX_BYTE8 11.9.13. DPRX_AUX_BYTE9 11.9.14. DPRX_AUX_BYTE10 11.9.15. DPRX_AUX_BYTE11 11.9.16. DPRX_AUX_BYTE12 11.9.17. DPRX_AUX_BYTE13 11.9.18. DPRX_AUX_BYTE14 11.9.19. DPRX_AUX_BYTE15 11.9.20. DPRX_AUX_BYTE16 11.9.21. DPRX_AUX_BYTE17 11.9.22. DPRX_AUX_BYTE18 11.9.23. DPRX_AUX_I2C0 11.9.24. DPRX_AUX_I2C1 11.9.25. DPRX_AUX_RESET 11.9.26. DPRX_AUX_HPD
11.12. Sink CV2AXI Registers x
11.12.1. Sink CV2AXI Registers Summary 11.12.2. Sink CV2AXI Registers Description
11.12.2. Sink CV2AXI Registers Description x
11.12.2.1. STATUS (0x50) 11.12.2.2. ACTIVE SAMPLE COUNT (0x52) 11.12.2.3. F0_ACTIVE_LINE_COUNT (0x53) 11.12.2.4. F1_ACTIVE_LINE_COUNT (0x54) 11.12.2.5. TOTAL_SAMPLE_COUNT (0x55) 11.12.2.6. F0_TOTAL_LINE_COUNT (0x56) 11.12.2.7. F1_TOTAL_LINE_COUNT (0x57) 11.12.2.8. COLOR_PATTERN (0x5C) 11.12.2.9. CONTROL (0x64)
1. DisplayPort Intel® FPGA IP Quick Reference
2. About This IP
3. Getting Started
4. DisplayPort Intel® FPGA IP Hardware Design Examples
5. DisplayPort Source
6. DisplayPort Sink
7. DisplayPort Intel® FPGA IP Parameters
8. DisplayPort Intel® FPGA IP Simulation Example
9. DisplayPort API Reference
10. DisplayPort Source Register Map and DPCD Locations
11. DisplayPort Sink Register Map and DPCD Locations
12. DisplayPort Intel® FPGA IP User Guide Archives
13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide

13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.18 23.1 20.0.1
  • Updated the 0x04 register and added 0x05 and 0x06 to the HDCP 2.3 TX Register Mapping table.
  • Updated the 0x40 register and added 0x44 and 0x45 to the HDCP 2.3 RX Register Mapping table.
  • Updated the HDCP Resource Utilization table by adding the HDCP resource data for Intel® Agilex™ 7 F-Tile devices.
  • Added DPTX_MST_ECF0 and DPTX_MST_ECF1 to the Source MST Registers chapter.
  • Updated the product family name to "Intel Agilex 7."
2022.10.20 22.3 20.0.1
  • Updated the Device Family Support section. Added the DisplayPort Intel FPGA IP Resource Utilization table and removed the following tables:
    • DisplayPort 1.4 Intel FPGA IP Resource Utilization
    • DisplayPort 2.0 Intel FPGA IP Resource Utilization
    • Intel Agilex FPGA IP Resource Utilization
  • Updated the TX Transceiver Interface section under DisplayPort Source to include the following figures:
    • DPTX IP parallel data mapping to 40 bits PMA width Transmitter Transceiver Parallel Data
    • DPTX IP parallel data mapping to 64 bits PMA width Transmitter Transceiver Parallel Data
  • Updated the Transceiver Reconfiguration Interface section under DisplayPort Source to include the Transceiver Reconfiguration for Different Design Variants table.
  • Updated the TX Transceiver Interface section under DisplayPort Sink to include the following figures:
    • DPRX IP parallel data mapping to 40 bits PMA width Receiver Transceiver Parallel Data
    • DPRX IP parallel data mapping to 64 bits PMA width Receiver Transceiver Parallel Data
  • Updated the Transceiver Reconfiguration Interface section under DisplayPort Sink to include the Transceiver Reconfiguration for Different Design Variants table.
2022.09.02 22.2 20.0.1 Added mentions of support for UHBR20 (20 Gbps) data rate where applicable throughout the document.
2022.07.20 22.2 20.0.1 Removed the following note for Support audio data channel from the table Sink Parameters:
  • The IP does not support audio data channel if you turn on the Support MST parameter.
2022.06.21 22.2 20.0.1 Updated the Verilog HDL CVI — DisplayPort Sink Example.
2022.04.29 22.1 20.0.1
  • Updated Table: DisplayPort Intel® FPGA IP Quick Reference.
  • Updated Figure: DisplayPort Source Top-Level Block Diagram.
  • Added Table: Video Interface (TX AXIS Video Interface).
  • Added new topic: Video Interface (Enable Active Video Data Protocols = AXIS-VVP Full) for DisplayPort Source and DisplayPort Sink.
  • Updated Figure: DisplayPort Sink Top-Level Block Diagram.
  • Updated Table: Video Interface (RX AXIS Video Interface).
  • Updated Table: DisplayPort Intel FPGA IP Source Parameters
  • Updated Table: DisplayPort Intel FPGA IP Sink Parameters
  • Added the following Section:
    • DisplayPort Source CV2AXI Register
    • DisplayPort Source CV2AXI Register Description
    • DisplayPort Source CV2AXI Register Summary
    • DisplayPort Sink CV2AXI Register
    • DisplayPort Sink CV2AXI Register Description
    • DisplayPort Sink CV2AXI Register Summary
2022.01.24 21.4 20.0.0
  • Added Intel® Agilex™ 7 support in Device Family Support topic.
  • Added support for DP2.0 for Intel® Stratix® 10 devices.
    • Updated DisplayPort Intel® FPGA IP Quick Reference topic.
    • Updated DisplayPort Terms and Acronyms topic.
    • Updated About This IP topic.
    • Updated Release Information topic.
    • Added new DP2.0 information in Performance and Resource Utilization topic.
    • Added new DP2.0 information in Main Data Path topic.
    • Added new DP2.0 information in Training and Link Quality Patterns Generator topic.
    • Added new DP2.0 information in TX Transceiver Interface topic.
    • Added new DP2.0 information in RX transceiver Interface topic.
    • Added new DP2.0 information in Secondary Stream Interface topic.
  • Updated Table: TX Transceiver Interface.
  • Updated Source Clock Tree topic.
  • Added a new topic: Calculating Video Bandwidth and Recovered Pixel Clock Frequency.
  • Added a new topic: IP to Transceiver Parallel Data Interface Width. in DisplayPort Source.
  • Added a new topic: Transceiver to IP Parallel Data Interface Width in DisplayPort Sink.
  • Added a new register in Table: DisplayPort Sink Capability Registers.
  • Added a new note in Table: Transceiver Management Interface.
  • Updated Table: RX Transceiver Interface.
  • Updated Table: rxN_msa_conduit Port Signals.
  • Updated Sink Clock Tree topic.
  • Updated DisplayPort Intel® FPGA IP Source Parameters table.
  • Updated DisplayPort Intel® FPGA IP Sink Parameters table.
  • Updated Table: btc_dptx_link_bw .
  • Updated Source General Registers topic.
  • Updated Sink General Registers topic.
2021.11.12 21.3 19.4.0
  • Updated Table: HDCP Resource Utilization for Support HDCP Key Management = 1
  • Updated Table: Source Parameters and Table: Sink Parameters for Support HDCP Key Management.
2021.05.11 21.1 19.3.0
  • Updated the Table: HDCP Interface in Source Interfaces and Sink Interfaces
    • Added information about Support HDCP Key Management for Conduit(Key) port type.
    • Added Avalon Memory-Mapped Port Type.
  • Update the Table DisplayPort Intel FPGA IP Source Parameters and DisplayPort Intel FPGA IP Sink Parameters to add Support HDCP Key Management parameter.
2021.01.20 20.2 19.3.0 Updated the DPTX_TX_CONTROL section:
  • Updated Table: DPTX_TX_CONTROL Bits to update the function description for bit 3:0.
2020.06.22 20.2 19.3.0
  • Updated HDCP feature support for Intel® Stratix® 10 devices.
    Note: The High-bandwidth Digital Content Protection (HDCP) feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
  • Updated the HDCP resource utilization data for Intel® Arria® 10 devices and added data for Intel® Stratix® 10 devices in the Performance and Resource Utilization section.
  • Updated the HDCP 1.3 Key Port address information in HDCP 1.3 TX Architecture and HDCP 1.3 RX Architecture sections.
  • Edited the maximum lane support information for Support HDCP 1.3 and Support HDCP 2.3 parameters in the Parameters section. The HDCP feature supports only maximum lane count of 4.
  • Added information about the tx_hdcp1_disable and tx_hdcp2_disable signals in the Source Interfaces section.
  • Added information about the rx_hdcp1_disable and rx_hdcp2_disable signals in the Sink Interfaces section.
2020.04.13 20.1 19.3.0
  • Updated the performance resource utilization information and included multi-stream transport (MST) data for Intel® Cyclone® 10 GX devices.
  • Added the following new sections to describe the DisplayPort sink non-GPU mode:
    • Sink Non-GPU Mode Support
    • Non-GPU Mode EDID Interface
  • Removed the HDCP Over DisplayPort Design Examples section. This information is now available in the DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide.
  • Added the following API functions:
    • btc_dprx_mst_link_addr_rep_set
    • btc_dprx_mst_conn_stat_notify_req
    • btc_dprx_mst_conn_stat_notify_rep
2020.01.20 19.4 19.2.0
  • Added a new section about High-bandwidth Digital Content Protection (HDCP). This feature is available only for Intel® Arria® 10 devices.
  • Added information about the following HDCP-related parameters in the DisplayPort Intel® FPGA IP Source Parameters and DisplayPort Intel® FPGA IP Sink Parameters sections:
    • Support HDCP 1.3
    • Support HDCP 2.3
  • Added information about HDCP-related signals in the Source Interfaces and Sink Interfaces sections.
  • Added information about a new design example that demonstrates the HDCP feature for Intel® Arria® 10 devices in the Intel® Quartus® Prime Pro Edition software.
2019.04.01 19.1 19.1
  • Added support for Intel® Stratix® 10 L-tile devices. Support for both Intel® Stratix® 10 L-tile and H-tile devices are final.
  • Added a table that lists the support for the Adaptive Sync feature by device family in the Device Family Support section. This feature is available only in the Intel® Quartus® Prime Pro Edition software.
2019.01.21 18.1 18.1
  • Added preliminary support for Intel® Stratix® 10 devices.
  • Removed the line that states that the IP supports multi-stream transport (MST) in Intel® Cyclone® 10 GX devices. The DisplayPort Intel® FPGA IP supports MST only in Intel® Arria® 10 devices in the current release.
  • Edited the performance resource utilization information to include data for Intel® Stratix® 10 devices and SST TX quad and MST data for Intel® Arria® 10 devices.
  • Adaptive sync feature is fully supported in version 18.1 onwards.
  • Updated the Core Features section to include support for HDR metadata transport using secondary stream data packet.
  • Updated the Secondary Stream Interface section to add information about using the secondary stream data packet to transport HDR metadata.
  • Edited the btc_dptx_baseaddr function information. The bit returns with the base address, and not 0 or 1.
  • Added a reference link to the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide.
2018.05.07 18.0 18.0
  • Renamed DisplayPort IP core to DisplayPort Intel® FPGA IP as part of standardizing and rebranding exercise.
  • Added reference link to the DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide.
  • Updated support for Intel® Cyclone® 10 GX device from advance to final.
  • Edited the performance resource utilization information to include Arria V GZ.
  • Add bit 0 and bit 127 to the Typical Secondary Stream Packet Flow diagram to indicate the direction of the streaming data.
  • Edited the btc_dptx_set_color_space function information to include the missing code.
  • Changed the typo in step 2 in the DisplayPort post link training adjust request flow (LQA). The offset 0x00101 bit [1] should be offset 0x00101 bit [5].
  • Added a note in the btc_dptx_set_color_space, btc_dptx_set_color_space, btc_dptxll_stream_set_color_space, DPTX0_MSA_COLOR, and DPRX0_MSA_COLOR topics to refer to Table 2–120 bit[3:0] in the VESA DisplayPort Standard version 1.4 for all colorimetry support including BT.2020.
  • Updated the video format information for btc_dptx_set_color_space, btc_dptx_mst_set_color_space, and btc_dptxll_stream_set_color_space functions. The format is 0 = RGB; 1 = YCbCr 4:4:4; 2 = YCbCr 4:2:2; 3 = YCbCr 4:2:0.
  • Edited typos in the following API functions:
    • btc_dptx_mst_conn_stat_notify_req
    • btc_dptx_mst_link_address_req
    • btc_dptx_mst_remote_dpcd_wr_req
    • btc_dptx_mst_remote_i2c_rd_req
    • btc_dptx_mst_set_color_space
    • btc_dptx_mst_tavgts_set
    • btc_dptxll_stream_set_pixel_rate
    • btc_dptxll_syslib_add_tx

Date

Version

Changes

November 2017 2017.11.06
  • Renamed DisplayPort IP core to Intel FPGA DisplayPort as per Intel rebranding.
  • Changed the term Qsys to Platform Designer.
  • Changed the term EyeQ to Eye Viewer as per Intel® rebranding.
  • Added advance support for Intel® Cyclone® 10 GX devices.
  • Updated information that the Intel FPGA DisplayPort core now conforms to Video Electronics Standards Association (VESA) DisplayPort Standard version 1.4.
  • Added data link rate support for HBR3 (8.10 Gbps). This rate is only available in quad symbols per clock for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices in the Intel® Quartus® Prime Pro Edition software.
  • Updated that the YCbCr 4:2:0 color format is fully supported starting 17.1 release.
  • Updated the Audio Interface section to clarify that the audio packing format complies to both IEC-60958-1 and IEC-60958-3 standards.
  • Moved information about the Intel FPGA DisplayPort design example parameters to the respective design example user guides.
  • Added a note in the Secondary Stream Interface sections about InfoFrame SDP support.
  • Edited the following registers:
    • DPRX_RX_CONTROL bits 10:8: Changed 111 from Reserved to Training pattern 4
    • DPRX_BER_CONTROL bits 1:0: Changed 00 to disparity error and code error counts and 10 to code error counts.
    • DPTX0_MSA_COLOUR bit 13: Added a note that if you configure this bit to use VSC SDP, refer to the VESA DisplayPort Standard version 1.4 for the VSC SDP Payload Pixel Encoding/Colorimetry Format. Y-Only and Raw format are not supported.
    • DPTX_RECONFIG bits 1 and 0: Clarified that these bits automatically clear (0) after one clock cycle.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Added preliminary support for adaptive sync feature and YCbCr 4:2:0 color format.
  • Updated the Device Family Support section with the recommended speed grades information.
  • Added input data ordering information for YCbCr 4:2:0 color format.
  • Added source support for proprietary video image format.
    • Added information about the TX Video IM Enable parameter. Turn on to enable the video image interface. Turn off to use the traditional HSYNC/VSYNC/DE video input interface.
    • Added information about the video image interface and a table showing comparison between the two interfaces.
  • Added information about rx_analog_reconfig interface for the sink's Transceiver Management Interface table.
  • Added a note in the Clocked Video Input Interface section that the example given uses Intel® 's Clocked Video Input IP core.
  • Added information that MST parameter now supports audio data channel.
October 2016 2016.10.31
  • Added information for the new Design Example parameters.
  • Removed all Arria 10 design example related information. For more information about Arria 10 design examples, refer to the DisplayPort IP Core Design Example User Guide.
  • Added information that MST parameter does not support audio data channel.
  • Added information about audio support for 2 symbols per clock.
  • Added information about DisplayPort MST source user application.
  • Updated information that the tx_analogreset[n–1:0], tx_digitalreset[n–1:0], rx_analogreset[n–1:0], and rx_digitalreset[n–1:0] signals are required only for Arria V, Cyclone V, and Stratix V devices.
  • Updated the API references.
  • Added new tx_idx parameter in TX API to support multiple TX instance.
  • Updated DisplayPort Sink and Source Register Map and DPCD locations.
May 2016 2016.05.02
  • Updated performance resource utilization information for 16.0 version.
  • Added a note that the audio feature is not supported in dual symbol mode for link rates.
  • Removed all information about TX MSA. The TX MSA will be automatically inserted by the DisplayPort source core.
    • Removed the Import fixed MSA parameter.
    • Removed the txN_msa_conduit signal.
  • Updated the DisplayPort source functional block diagram and updated or included information for the related paths:
    • Main link data path
    • Video packetizer path
    • Video geometry measurement path
    • Audio and secondary stream encoder path
    • Training and link quality patterns generator
  • Added new information for DisplayPort source:
    • Controller interface
    • Sideband channel
  • Updated the source audio interface section to include information about 1-channel audio over 2-channel audio and 3-channel audio over 8-channel audio.
  • Updated video data format information for the DisplayPort source and sink cores.
  • Added support for black video feature for DisplayPort sink core.
  • Updated the Typical Secondary Stream Packet diagram for DisplayPort sink - changed data [127:0] to data [159:0].
  • Updated the DPTX_TX_CONTROL source register.
  • Added new information for DisplayPort hardware demonstration:
    • DisplayPort Link Training Flow
    • DisplayPort Post Link Training Adjust Request Flow (LQA)
  • Added links to archived versions of the DisplayPort IP Core User Guide.
November 2015 2015.11.02
  • Changed instances of Quartus II to Intel® Quartus® Prime .
  • Updated performance resource utilization information for 15.1 version.
  • Removed information about tx_vid_f. The tx_vid_f pin is removed from the DisplayPort IP core because the signal is now handled internally by the core..
  • Added a new port, rx_restart, for RX transceiver interface. This port resets the RX PHY reset controller when RX data loses alignment. Only applicable for Arria 10 devices.
  • Added specific settings for Arria 10 Transceiver Native PHY, and Arria 10 hardware demonstration files for the DisplayPort hardware demonstration.
  • Added a new DisplayPort API function, btc_dptx_hpd_change.
May 2015 2015.05.04
  • Added Arria 10 support.
  • Updated color support:
    • RGB—18, 24, 30, 36, or 48 bpp
    • YCbCr 4:4:4—24, 30, 36, or 48 bpp
    • YCbCr 4:2:2—16, 20, 24, or 32 bpp
  • Removed information about Link Quality Generation register. These bits are now combined into the DPTX_TX_CONTROL register.
  • Added information about DPTX_TEST_80BIT_PATTERN1-3 bits.
  • Added source-supported DPCD locations.
  • Added new sink-supported DPCD location bits: TEST_REQUEST, TEST_LINK_RATE, TEST_LANE_COUNT, PHY_TEST_PATTERN, and TEST_80BIT_CUSTOM_PATTERN.
  • Added Arria 10 information for the DisplayPort IP core hardware demonstration and simulation example.
December 2014 2014.12.30 Edited the DisplayPort RX link rate (Clock Recovery interface) for HBR2 from 4.50 Gbps to 5.40 Gbps.
December 2014 2014.12.15
  • Added information about multi-stream support (MST, 1 to 4 source and sink streams). You can access this feature using these parameters:
    • Support MST
    • Max stream count
  • Added support for 4Kp60 resolution.
  • Added information about clock recovery feature for the hardware demonstration.
  • Removed information for double reference clocks (162MHz and 270MHz) for transceiver clocking. The IP core no longer supports double reference clocks.
  • Added new source registers:
    • 0x00a0 (DPTX_MST_CONTROL1)
    • 0x00a2 (DPTX_MST_VCPTAB0)
    • 0x00a3 (DPTX_MST_VCPTAB)
    • 0x00a3 (DPTX_MST_VCPTAB1)
    • 0x00a4 (DPTX_MST_VCPTAB2)
    • 0x00a5 (DPTX_MST_VCPTAB3)
    • 0x00a6 (DPTX_MST_VCPTAB4)
    • 0x00a7 (DPTX_MST_VCPTAB5)
    • 0x00a8 (DPTX_MST_VCPTAB6)
    • 0x00a9 (DPTX_MST_VCPTAB7)
    • 0x00aa (DPTX_MST_TAVG_TS)
  • Added new sink registers:
    • 0x0006 (DPRX_BER_CNTI0)
    • 0x0007 (DPRX_BER_CNTI1)
    • 0x00a0 (DPRX_MST_CONTROL1)
    • 0x00a1 (DPRX_MST_STATUS1)
    • 0x00a2 (DPRX_MST_VCPTAB0)
    • 0x00a3 (DPRX_MST_VCPTAB1)
    • 0x00a4 (DPRX_MST_VCPTAB2)
    • 0x00a5 (DPRX_MST_VCPTAB3)
    • 0x00a6 (DPRX_MST_VCPTAB4)
    • 0x00a7 (DPRX_MST_VCPTAB5)
    • 0x00a8 (DPRX_MST_VCPTAB6)
    • 0x00a9 (DPRX_MST_VCPTAB7)
  • Changed the value of the following source register bits:
    • 0x0000 - Bits RX_LINK_RATE
    • 0x0001 - Bits RX_LINK_RATE
    • 0x0002 - Bits RSTI3, RSTI2, RSTI1, RSTI0
  • Added new signals:
    clk_cal Calibration clock for transceiver management interface

    tx_link_rate_8bits

    rx_link_rate_8bits

    		Main link rate expressed in multiples of 270Mbps —

    txN_video_in

    txN_vid_clk

    txN_audio

    txN_audio_clk

    txN_ss

    txN_msa_conduit

    		TX signals for Stream 1, 2, and 3

    rxN_video_out

    rxN_vid_clk

    rxN_audio

    rxN_ss

    rxN_msa_conduit

    rxN_stream

    		RX signals for Stream 1, 2, and 3
  • Changed the following signal names:
    • rx_xcvr_clkout to rx_ss_clk
    • tx_xcvr_clkout to tx_ss_clk
June 2014 2014.06.30
  • Native PHY is removed from the IP core; included information about how to instantiate the PHY outside the DisplayPort IP core.
  • Updated the source and sink block diagrams.
  • Updated the source and sink register map information.
  • Added new sink register bits:
    • LQA ACTIVE
    • PHY_SINK_TEST_LANE_SEL
    • PHY_SINK_TEST_LANE_EN
    • AUX_IRQ_EN
    • TX_STROBE
    • DPRX_AUX_STATUS bits
    • DPRX_AUX_I2C0 bits
    • DPRX_AUX_I2C0 bits
    • DPRX_AUX_HPD bits
  • Removed these sink register bits:
    • HPD_IRQ
    • HPD_EN
    • DPRX_AUX_IRQ_EN bits
  • Added a new source register bit:
    • VTOTAL
  • Added source TX transceiver interface signals
  • Removed these source signals:
    • xcvr_refclk
    • tx_serial_data
    • xcvr_reconfig
  • Added sink audio and RX transceiver interface signals.
  • Removed these sink signals:
    • xcvr_refclk
    • rx_serial_data
    • xcvr_reconfig
  • Added information about Transceiver Reconfiguration Interface for source and sink.
  • Added information about single clock reference (135 MHz) for source and sink.
  • Added information about Bitec HSMC DisplayPort daughter card in the Hardware Demonstration chapter.
  • Updated the API reference.

November 2013

13.1

  • Updated the source and sink register map information.
  • Added dual and quad pixel mode support.
  • Added support for quad symbol (40-bit) transceiver data interface.
  • Added support for Cyclone V devices.
  • Added HBR2 support for Arria V and Arria V GZ devices.
  • Added information about eDP support.
  • Updated the API reference.

May 2013

13.0

  • Added information on audio support.
  • Added HBR2 support for Stratix V devices.
  • Added information on secondary data support.

February 2013

12.1 SP1 (Beta)

Second beta release:

  • Updated the filenames for the hardware demonstration and simulation example.
  • Added chapter describing the IP core’s compilation example.
  • Miscellaneous updates.

December 2012

12.1

(Beta)

Initial beta release.

Level Two Title