Embedded Peripherals IP User Guide

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ID 683130
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core
1. Introduction x
1.1. Tool Support 1.2. Device Support 1.3. Embedded Peripherals IP User Guide Archives 1.4. Document Revision History for Embedded Peripherals IP User Guide
2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores x
2.1. Core Overview 2.2. Functional Description 2.3. Parameters 2.4. Register Description 2.5. Avalon® -ST Single-Clock and Dual-Clock FIFO Core Revision History
2.2. Functional Description x
2.2.1. Interfaces 2.2.2. Operating Modes 2.2.3. Fill Level 2.2.4. Thresholds
3. Avalon® -ST Serial Peripheral Interface Core x
3.1. Functional Description 3.2. Configuration 3.3. Avalon® -ST Serial Peripheral Interface Core Revision History
3.1. Functional Description x
3.1.1. Interfaces 3.1.2. Operation 3.1.3. Timing 3.1.4. Limitations
4. SPI Core x
4.1. Core Overview 4.2. Functional Description 4.3. Configuration 4.4. Software Programming Model 4.5. Example Test Code 4.6. SPI Core Revision History
4.2. Functional Description x
4.2.1. Example Configurations 4.2.2. Transmitter Logic 4.2.3. Receiver Logic 4.2.4. Host and Agent Modes
4.2.4. Host and Agent Modes x
4.2.4.1. Host Mode Operation 4.2.4.2. Agent Mode Operation 4.2.4.3. Multi-Agent Environments
4.3. Configuration x
4.3.1. Host/Agent Settings 4.3.2. Data Register Settings 4.3.3. Timing Settings 4.3.4. Synchronizer Stages
4.3.1. Host/Agent Settings x
4.3.1.1. Number of Select (SS_n) Signals 4.3.1.2. SPI Clock (sclk) Rate 4.3.1.3. Specify Delay
4.4. Software Programming Model x
4.4.1. Hardware Access Routines 4.4.2. Software Files 4.4.3. Register Map
4.4.1. Hardware Access Routines x
4.4.1.1. alt_avalon_spi_command()
4.4.3. Register Map x
4.4.3.1. rxdata Register 4.4.3.2. txdata Register 4.4.3.3. status Register 4.4.3.4. control Register 4.4.3.5. slaveselect Register 4.4.3.6. end of packet value Register
5. SPI Agent/JTAG to Avalon® Host Bridge Cores x
5.1. Core Overview 5.2. Functional Description 5.3. Parameters 5.4. SPI Agent/JTAG to Avalon® Host Bridge Cores Revision History
6. Intel eSPI Agent Core x
6.1. Functional Description 6.2. Resource Utilization 6.3. IP Parameters 6.4. Interface Signals 6.5. Registers 6.6. Peripheral Channel Avalon Interface Use Model 6.7. Intel eSPI Agent Core Revision History
6.1. Functional Description x
6.1.1. Link Layer 6.1.2. Transaction Layer 6.1.3. Channel Specific Layer 6.1.4. Port80 Implementation 6.1.5. VW message to Physical Port Implementation 6.1.6. Avalon® Memory-Mapped Interface Settings
6.1.3. Channel Specific Layer x
6.1.3.1. Peripheral Channel 6.1.3.2. Virtual Wire Channel
6.1.3.2. Virtual Wire Channel x
6.1.3.2.1. Interrupt Event
6.5. Registers x
6.5.1. Avalon® memory-mapped interface Accessible Registers 6.5.2. eSPI Interface Accessible Registers
6.5.1. Avalon® memory-mapped interface Accessible Registers x
6.5.1.1. Status Register 6.5.1.2. Control Register 6.5.1.3. Error Register
6.5.2. eSPI Interface Accessible Registers x
6.5.2.1. eSPI Status Register 6.5.2.2. Capabilities and Configuration Registers
7. eSPI to LPC Bridge Core x
7.1. Unsupported LPC Features 7.2. IP Parameters 7.3. Supported IP Clock Frequency 7.4. Functional Description 7.5. Interface Signals 7.6. Registers 7.7. eSPI to LPC Bridge Core Revision History
7.4. Functional Description x
7.4.1. FIFO Implementation 7.4.2. Transaction Ordering Rule 7.4.3. eSPI Command to LPC Cycle Type Conversion 7.4.4. SERIRQ Interrupt Event
7.6. Registers x
7.6.1. Status Register 7.6.2. Error Register
8. Ethernet MDIO Core x
8.1. Core Overview 8.2. Functional Description 8.3. Parameter 8.4. Configuration Registers 8.5. Interface Signals 8.6. Ethernet MDIO Core Revision History
8.2. Functional Description x
8.2.1. MDIO Frame Format (Clause 45) 8.2.2. MDIO Clock Generation 8.2.3. Interfaces 8.2.4. Operation
8.2.4. Operation x
8.2.4.1. Write Operation 8.2.4.2. Read Operation
9. Intel FPGA 16550 Compatible UART Core x
9.1. Core Overview 9.2. Feature Description 9.3. Software Programming Model 9.4. Address Map and Register Descriptions 9.5. Intel FPGA 16550 Compatible UART Core Revision History
9.2. Feature Description x
9.2.1. Unsupported Features 9.2.2. Interface 9.2.3. General Architecture 9.2.4. 16550 UART General Programming Flow Chart 9.2.5. Configuration Parameters 9.2.6. DMA Support 9.2.7. FPGA Resource Usage 9.2.8. Timing and Fmax 9.2.9. Avalon® -MM Agent 9.2.10. Over-run/Under-run Conditions 9.2.11. Hardware Auto Flow-Control 9.2.12. Clock and Baud Rate Selection
9.2.9. Avalon® -MM Agent x
9.2.9.1. Read behavior 9.2.9.2. Write behavior
9.2.10. Over-run/Under-run Conditions x
9.2.10.1. Overrun 9.2.10.2. Receive Overrun Behavior 9.2.10.3. Transmit Overrun Behavior 9.2.10.4. Underrun
9.3. Software Programming Model x
9.3.1. Overview 9.3.2. Supported Features 9.3.3. Unsupported Features 9.3.4. Configuration 9.3.5. 16550 UART API 9.3.6. Driver Examples
9.3.5. 16550 UART API x
9.3.5.1. Public APIs 9.3.5.2. Private APIs 9.3.5.3. UART Device Structure
9.4. Address Map and Register Descriptions x
9.4.1. rbr_thr_dll 9.4.2. ier_dlh 9.4.3. iir 9.4.4. fcr 9.4.5. lcr 9.4.6. mcr 9.4.7. lsr 9.4.8. msr 9.4.9. scr 9.4.10. afr 9.4.11. tx_low
10. UART Core x
10.1. Core Overview 10.2. Functional Description 10.3. Instantiating the Core 10.4. Software Programming Model 10.5. UART Core Revision History
10.2. Functional Description x
10.2.1. Avalon® -MM Agent Interface and Registers 10.2.2. RS-232 Interface 10.2.3. Transmitter Logic 10.2.4. Receiver Logic 10.2.5. Baud Rate Generation
10.3. Instantiating the Core x
10.3.1. Configuration Settings 10.3.2. Simulation Settings
10.3.1. Configuration Settings x
10.3.1.1. Baud Rate Options 10.3.1.2. Baud Rate (bps) Setting 10.3.1.3. Baud Rate Can Be Changed By Software Setting 10.3.1.4. Data Bits, Stop Bits, Parity 10.3.1.5. Synchronizer Stages 10.3.1.6. Streaming Data (DMA) Control
10.3.1.6. Streaming Data (DMA) Control x
10.3.1.6.1. Include End-of-Packet Register
10.3.2. Simulation Settings x
10.3.2.1. Simulated Transmitter Baud Rate 10.3.2.2. Simulation Considerations
10.4. Software Programming Model x
10.4.1. HAL System Library Support 10.4.2. Software Files 10.4.3. Register Map 10.4.4. Interrupt Behavior
10.4.1. HAL System Library Support x
10.4.1.1. Driver Options: Fast vs Small Implementations 10.4.1.2. ioctl() Operations 10.4.1.3. Limitations
10.4.1.1. Driver Options: Fast vs Small Implementations x
10.4.1.1.1. UART API 10.4.1.1.2. UART Device Structure
10.4.3. Register Map x
10.4.3.1. rxdata Register 10.4.3.2. txdata Register 10.4.3.3. status Register 10.4.3.4. control Register 10.4.3.5. divisor Register (Optional) 10.4.3.6. endofpacket Register (Optional)
11. JTAG UART Core x
11.1. Core Overview 11.2. Functional Description 11.3. Configuration 11.4. Software Programming Model 11.5. JTAG UART Core Revision History
11.2. Functional Description x
11.2.1. Avalon® Agent Interface and Registers 11.2.2. Read and Write FIFOs 11.2.3. JTAG Interface 11.2.4. Host-Target Connection 11.2.5. Operating System Code Page
11.3. Configuration x
11.3.1. Configuration Page
11.3.1. Configuration Page x
11.3.1.1. Write FIFO Settings 11.3.1.2. Read FIFO Settings
11.4. Software Programming Model x
11.4.1. HAL System Library Support 11.4.2. Software Files 11.4.3. Accessing the JTAG UART Core via a Host PC 11.4.4. Register Map 11.4.5. Interrupt Behavior
11.4.1. HAL System Library Support x
11.4.1.1. Driver Options: Fast vs. Small Implementations 11.4.1.2. ioctl() Operations
11.4.4. Register Map x
11.4.4.1. Data Register 11.4.4.2. Control Register
12. Intel FPGA Avalon® Mailbox Core x
12.1. Core Overview 12.2. Functional Description 12.3. Interface 12.4. HAL Driver 12.5. Intel FPGA Avalon® Mailbox Core Revision History
12.2. Functional Description x
12.2.1. Message Sending and Retrieval Process 12.2.2. Component Register Map
12.2.2. Component Register Map x
12.2.2.1. Command Register 12.2.2.2. Pointer Register 12.2.2.3. Status Register 12.2.2.4. Interrupt Masking Register
12.3. Interface x
12.3.1. Component Interface 12.3.2. Component Parameterization
12.4. HAL Driver x
12.4.1. Feature Description
12.4.1. Feature Description x
12.4.1.1. Component Configuration 12.4.1.2. Driver Implementation 12.4.1.3. Driver Examples
12.4.1.1. Component Configuration x
12.4.1.1.1. Interrupt Mode 12.4.1.1.2. Polling Mode
13. Intel FPGA Avalon® Mutex Core x
13.1. Core Overview 13.2. Functional Description 13.3. Configuration 13.4. Software Programming Model 13.5. Mutex API 13.6. Intel FPGA Avalon® Mutex Core Revision History
13.4. Software Programming Model x
13.4.1. Software Files 13.4.2. Hardware Access Routines
13.5. Mutex API x
13.5.1. altera_avalon_mutex_is_mine() 13.5.2. altera_avalon_mutex_first_lock() 13.5.3. altera_avalon_mutex_lock() 13.5.4. altera_avalon_mutex_open() 13.5.5. altera_avalon_mutex_trylock() 13.5.6. altera_avalon_mutex_unlock()
14. Intel FPGA Avalon® I2C (Host) Core x
14.1. Core Overview 14.2. Feature Description 14.3. Configuration Parameters 14.4. Interface 14.5. Registers 14.6. Reset and Clock Requirements 14.7. Functional Description 14.8. Intel FPGA Avalon® I2C (Host) Core API 14.9. Intel FPGA Avalon® I2C (Host) Core Revision History
14.2. Feature Description x
14.2.1. Supported Features 14.2.2. Unsupported Features
14.5. Registers x
14.5.1. Register Memory Map 14.5.2. Register Descriptions
14.5.2. Register Descriptions x
14.5.2.1. Transfer Command FIFO (TFR_CMD) 14.5.2.2. Receive Data FIFO (RX_DATA) 14.5.2.3. Control Register (CTRL) 14.5.2.4. Interrupt Status Enable Register (ISER) 14.5.2.5. Interrupt Status Register (ISR) 14.5.2.6. Status Register (STATUS) 14.5.2.7. TFR CMD FIFO Level (TFR CMD FIFO LVL) 14.5.2.8. RX Data FIFO Level (RX Data FIFO LVL) 14.5.2.9. SCL Low Count (SCL LOW) 14.5.2.10. SCL High Count (SCL HIGH) 14.5.2.11. SDA Hold Count (SDA HOLD)
14.7. Functional Description x
14.7.1. Overview 14.7.2. Configuring TFT_CMD Register Examples 14.7.3. I2C Serial Interface Connection 14.7.4. Avalon® -MM Agent Interface 14.7.5. Avalon® -ST Interface 14.7.6. Programming Model
14.7.2. Configuring TFT_CMD Register Examples x
14.7.2.1. 7-bit Addressing Mode 14.7.2.2. 10-bit Addressing Mode
14.7.2.1. 7-bit Addressing Mode x
14.7.2.1.1. Host Transmitter Writes 2 Bytes to Agent Receiver 14.7.2.1.2. Host Receiver Reads 2 Bytes from Agent Transmitter 14.7.2.1.3. Combine Format (Host Writes 1 Byte and Changes Direction to Read 2 Bytes)
14.7.2.2. 10-bit Addressing Mode x
14.7.2.2.1. Host Transmitter Writes 2 Bytes to Agent Receiver 14.7.2.2.2. Host Receiver Reads 2 Bytes from Agent Transmitter
14.8. Intel FPGA Avalon® I2C (Host) Core API x
14.8.1. Optional Status Retrieval API
15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core x
15.1. Core Overview 15.2. Functional Description 15.3. Platform Designer Parameters 15.4. Signals 15.5. How to Translate the Bridge's I2C Data and I2C I/O Ports to an I2C Interface 15.6. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core Revision History
15.2. Functional Description x
15.2.1. Block Diagram 15.2.2. N-byte Addressing 15.2.3. N-byte Addressing with N-bit Address Stealing 15.2.4. Read Operation 15.2.5. Write Operation 15.2.6. Interacting with Multi-Hosts
15.2.4. Read Operation x
15.2.4.1. Random Address Read 15.2.4.2. Sequential Address Read 15.2.4.3. Current Address Read
16. Intel FPGA Avalon® Compact Flash Core x
16.1. Core Overview 16.2. Functional Description 16.3. Required Connections 16.4. Software Programming Model 16.5. Intel FPGA Avalon® Compact Flash Core Revision History
16.4. Software Programming Model x
16.4.1. HAL System Library Support 16.4.2. Software Files 16.4.3. Register Maps
16.4.3. Register Maps x
16.4.3.1. Ide Registers 16.4.3.2. Ctl Registers 16.4.3.3. Cfctl Register 16.4.3.4. idectl Register
17. EPCS/EPCQA Serial Flash Controller Core x
17.1. Core Overview 17.2. Functional Description 17.3. Configuration 17.4. Interface Signals 17.5. Software Programming Model 17.6. Driver API 17.7. EPCS/EPCQA Serial Flash Controller Core Revision History
17.2. Functional Description x
17.2.1. Avalon® -MM Agent Interface and Registers
17.5. Software Programming Model x
17.5.1. HAL System Library Support 17.5.2. Software Files
18. Intel FPGA Serial Flash Controller Core x
18.1. Parameters 18.2. Registers 18.3. Nios® II and Nios® V Tools Support 18.4. Driver API 18.5. Intel FPGA Serial Flash Controller Core Revision History
18.1. Parameters x
18.1.1. Configuration Device Types 18.1.2. I/O Mode 18.1.3. Chip Selects 18.1.4. Interface Signals
18.2. Registers x
18.2.1. Register Memory Map 18.2.2. Register Descriptions
18.2.2. Register Descriptions x
18.2.2.1. FLASH_RD_STATUS 18.2.2.2. FLASH_RD_SID 18.2.2.3. FLASH_RD_RDID 18.2.2.4. FLASH_MEM_OP 18.2.2.5. FLASH_ISR 18.2.2.6. FLASH_IMR 18.2.2.7. FLASH_CHIP_SELECT
18.2.2.4. FLASH_MEM_OP x
18.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
18.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
18.2.2.4.1.1. Sector Protect 18.2.2.4.1.2. Sector Erase
18.3. Nios® II and Nios® V Tools Support x
18.3.1. Booting Nios® II from Flash 18.3.2. Nios® II and Nios® V HAL Drivers
18.3.1. Booting Nios® II from Flash x
18.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier 18.3.1.2. Boot Copier File 18.3.1.3. When Nios® II SBT will Append a Boot Copier 18.3.1.4. Creating HEX Programming File 18.3.1.5. Programming the Flash 18.3.1.6. Custom Boot Copiers 18.3.1.7. Executing in Place
19. Intel FPGA Serial Flash Controller II Core x
19.1. Parameters 19.2. Registers 19.3. Nios® II and Nios® V Tools Support 19.4. Driver API 19.5. Intel FPGA Serial Flash Controller II Core Revision History
19.1. Parameters x
19.1.1. Configuration Device Types 19.1.2. I/O Mode 19.1.3. Chip Selects 19.1.4. Interface Signals
19.2. Registers x
19.2.1. Register Memory Map 19.2.2. Register Descriptions
19.2.2. Register Descriptions x
19.2.2.1. FLASH_RD_STATUS 19.2.2.2. FLASH_RD_RDID 19.2.2.3. FLASH_MEM_OP 19.2.2.4. FLASH_CHIP_SELECT 19.2.2.5. EPCQ_FLAG_STATUS 19.2.2.6. DEVICE_ID_DATA_x
19.2.2.3. FLASH_MEM_OP x
19.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
19.2.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
19.2.2.3.1.1. Sector Protect 19.2.2.3.1.2. Sector Erase
19.3. Nios® II and Nios® V Tools Support x
19.3.1. Booting Nios® II from Flash 19.3.2. Nios® II and Nios® V HAL Drivers
19.3.1. Booting Nios® II from Flash x
19.3.1.1. Flash Memory Map and Setting Nios® II Reset Vector when Using a Boot Copier 19.3.1.2. Boot Copier File 19.3.1.3. When Nios® II SBT will Append a Boot Copier 19.3.1.4. Creating HEX Programming File 19.3.1.5. Programming the Flash 19.3.1.6. Custom Boot Copiers 19.3.1.7. Executing in Place
20. Intel FPGA Generic QUAD SPI Controller Core x
20.1. Parameters 20.2. Registers 20.3. Nios® II and Nios® V Tools Support 20.4. Driver API 20.5. Intel FPGA Generic QUAD SPI Controller Core Revision History
20.1. Parameters x
20.1.1. Configuration Device Types 20.1.2. I/O Mode 20.1.3. Chip Selects 20.1.4. Interface Signals
20.2. Registers x
20.2.1. Register Memory Map 20.2.2. Register Descriptions
20.2.2. Register Descriptions x
20.2.2.1. FLASH_RD_STATUS 20.2.2.2. FLASH_RD_SID 20.2.2.3. FLASH_RD_RDID 20.2.2.4. FLASH_MEM_OP 20.2.2.5. FLASH_ISR 20.2.2.6. FLASH_IMR 20.2.2.7. FLASH_CHIP_SELECT
20.2.2.4. FLASH_MEM_OP x
20.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command
20.2.2.4.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
20.2.2.4.1.1. Sector Protect 20.2.2.4.1.2. Sector Erase
20.3. Nios® II and Nios® V Tools Support x
20.3.1. Nios® II and Nios® V HAL Drivers
21. Intel FPGA Generic QUAD SPI Controller II Core x
21.1. Parameters 21.2. Interface Signals 21.3. Registers 21.4. Nios® II and Nios® V Tools Support 21.5. Driver API 21.6. Intel FPGA Generic QUAD SPI Controller II Core Revision History
21.1. Parameters x
21.1.1. Disable Dedicated Active Serial Interface 21.1.2. Enable SPI Pins Interface 21.1.3. Enable Flash Simulation Model 21.1.4. Configuration Device Types 21.1.5. I/O Mode 21.1.6. Chip Selects
21.3. Registers x
21.3.1. Register Memory Map 21.3.2. Register Descriptions
21.3.2. Register Descriptions x
21.3.2.1. FLASH_RD_STATUS 21.3.2.2. FLASH_RD_RDID 21.3.2.3. FLASH_MEM_OP 21.3.2.4. FLASH_CHIP_SELECT 21.3.2.5. EPCQ_FLAG_STATUS 21.3.2.6. DEVICE_ID_DATA_x
21.3.2.3. FLASH_MEM_OP x
21.3.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command
21.3.2.3.1. Valid Sector Combination for Sector Protect and Sector Erase Command x
21.3.2.3.1.1. Sector Protect 21.3.2.3.1.2. Sector Erase
21.4. Nios® II and Nios® V Tools Support x
21.4.1. Nios® II and Nios® V HAL Drivers
22. Interval Timer Core x
22.1. Core Overview 22.2. Functional Description 22.3. Configuration 22.4. Software Programming Model 22.5. Interval Timer Core API 22.6. Interval Timer Core Revision History
22.2. Functional Description x
22.2.1. Avalon® -MM Agent Interface
22.3. Configuration x
22.3.1. Timeout Period 22.3.2. Counter Size 22.3.3. Hardware Options 22.3.4. Configuring the Timer as a Watchdog Timer
22.4. Software Programming Model x
22.4.1. HAL System Library Support 22.4.2. Software Files 22.4.3. Register Map 22.4.4. Interrupt Behavior
23. Intel FPGA Avalon FIFO Memory Core x
23.1. Core Overview 23.2. Functional Description 23.3. Configuration 23.4. Software Programming Model 23.5. Programming with the Intel FPGA Avalon FIFO Memory 23.6. Intel FPGA Avalon FIFO Memory API 23.7. Intel FPGA Avalon FIFO Memory Core Revision History
23.2. Functional Description x
23.2.1. Avalon® -MM Write Agent to Avalon® -MM Read Agent 23.2.2. Avalon® -ST Sink to Avalon® -ST Source 23.2.3. Avalon® -MM Write Agent to Avalon® -ST Source 23.2.4. Avalon® -ST Sink to Avalon® -MM Read Agent 23.2.5. Status Interface 23.2.6. Clocking Modes
23.3. Configuration x
23.3.1. FIFO Settings 23.3.2. Interface Parameters 23.3.3. Interface Signals
23.4. Software Programming Model x
23.4.1. HAL System Library Support 23.4.2. Software Files
23.5. Programming with the Intel FPGA Avalon FIFO Memory x
23.5.1. Software Control 23.5.2. Software Example
23.6. Intel FPGA Avalon FIFO Memory API x
23.6.1. altera_avalon_fifo_init() 23.6.2. altera_avalon_fifo_read_status() 23.6.3. altera_avalon_fifo_read_ienable() 23.6.4. altera_avalon_fifo_read_almostfull() 23.6.5. altera_avalon_fifo_read_almostempty() 23.6.6. altera_avalon_fifo_read_event() 23.6.7. altera_avalon_fifo_read_level() 23.6.8. altera_avalon_fifo_clear_event() 23.6.9. altera_avalon_fifo_write_ienable() 23.6.10. altera_avalon_fifo_write_almostfull() 23.6.11. altera_avalon_fifo_write_almostempty() 23.6.12. altera_avalon_write_fifo() 23.6.13. altera_avalon_write_other_info() 23.6.14. altera_avalon_fifo_read_fifo() 23.6.15. altera_avalon_fifo_read_other_info()
24. On-Chip Memory (RAM and ROM) Intel FPGA IP x
24.1. Core Overview 24.2. Component-Level Design for On-Chip Memory 24.3. Platform Designer System-Level Design for On-Chip Memory 24.4. Simulation for On-Chip Memory 24.5. Quartus® Prime Project-Level Design for On-Chip Memory 24.6. Board-Level Design for On-Chip Memory 24.7. Example Design with On-Chip Memory 24.8. On-Chip Memory (RAM and ROM) Intel FPGA IP Revision History
24.2. Component-Level Design for On-Chip Memory x
24.2.1. Memory Type 24.2.2. Size 24.2.3. Read Latency 24.2.4. ROM/RAM Memory Protection 24.2.5. ECC Parameter 24.2.6. Memory Initialization
25. On-Chip Memory II (RAM or ROM) Intel FPGA IP x
25.1. Core Overview 25.2. Embedded Memory Architecture and Features 25.3. Component-Level Configurations 25.4. Interface Signals 25.5. Control and Status Registers 25.6. Software Programming Model 25.7. Platform Designer System-Level Design for On-Chip Memory II 25.8. Simulation for On-Chip Memory II 25.9. Quartus® Prime Project-Level Design for On-Chip Memory II 25.10. Board-Level Design for On-Chip Memory II 25.11. Example Design with On-Chip Memory II 25.12. On-Chip Memory II (RAM and ROM) Intel FPGA IP Revision History
25.3. Component-Level Configurations x
25.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration 25.3.2. AXI-4 On-Chip Memory II Configuration
25.3.1. Avalon Memory-Mapped On-Chip Memory II Configuration x
25.3.1.1. Avalon Memory-Mapped Interface 25.3.1.2. Memory Type 25.3.1.3. Clock Enable 25.3.1.4. Size 25.3.1.5. Read During Write Mode 25.3.1.6. Read Latency 25.3.1.7. ROM/RAM Memory Protection 25.3.1.8. ECC 25.3.1.9. Memory Initialization
25.3.2. AXI-4 On-Chip Memory II Configuration x
25.3.2.1. AXI-4 Interface 25.3.2.2. Memory Type 25.3.2.3. Clock Enable 25.3.2.4. Size 25.3.2.5. Read During Write Mode 25.3.2.6. ROM/RAM Memory Protection 25.3.2.7. Memory Initialization 25.3.2.8. ECC
25.3.2.8. ECC x
25.3.2.8.1. Supported ECC Configuration 25.3.2.8.2. Supported ECC Features 25.3.2.8.3. ECC Status Reporting 25.3.2.8.4. ECC Encoder Bypass 25.3.2.8.5. Read Modify Write
25.4. Interface Signals x
25.4.1. Avalon Memory-Mapped Interface Signals 25.4.2. Avalon Memory-Mapped Interface Timing Diagram 25.4.3. AXI-4 Lite Interface Signals 25.4.4. AXI-4 Interface Signals 25.4.5. AXI Interface Timing Diagram
25.5. Control and Status Registers x
25.5.1. Register Memory Map 25.5.2. Register Descriptions
25.6. Software Programming Model x
25.6.1. Read ECC Error Status FIFO 25.6.2. Enable Encoder Bypass Feature
26. Optrex 16207 LCD Controller Core x
26.1. Core Overview 26.2. Functional Description 26.3. Software Programming Model 26.4. Optrex 16207 LCD Controller Core Revision History
26.3. Software Programming Model x
26.3.1. HAL System Library Support 26.3.2. Displaying Characters on the LCD 26.3.3. Software Files 26.3.4. Register Map 26.3.5. Interrupt Behavior
27. PIO Core x
27.1. Core Overview 27.2. Functional Description 27.3. Example Configurations 27.4. Configuration 27.5. Software Programming Model 27.6. PIO Core Revision History
27.2. Functional Description x
27.2.1. Data Input and Output 27.2.2. Edge Capture 27.2.3. IRQ Generation
27.3. Example Configurations x
27.3.1. Avalon® -MM Interface
27.4. Configuration x
27.4.1. Basic Settings 27.4.2. Input Options 27.4.3. Simulation
27.4.1. Basic Settings x
27.4.1.1. Width 27.4.1.2. Direction 27.4.1.3. Output Port Reset Value 27.4.1.4. Output Register
27.4.2. Input Options x
27.4.2.1. Edge Capture Register 27.4.2.2. Interrupt
27.5. Software Programming Model x
27.5.1. Software Files 27.5.2. Register Map 27.5.3. Interrupt Behavior 27.5.4. Software Files
27.5.2. Register Map x
27.5.2.1. data Register 27.5.2.2. direction Register 27.5.2.3. interruptmask Register 27.5.2.4. edgecapture Register 27.5.2.5. outset and outclear Register
28. PLL Cores x
28.1. Core Overview 28.2. Functional Description 28.3. Instantiating the Avalon® ALTPLL Core 28.4. Instantiating the PLL Core 28.5. Hardware Simulation Considerations 28.6. Register Definitions and Bit List 28.7. PLL Cores Revision History
28.2. Functional Description x
28.2.1. ALTPLL IP Core 28.2.2. Clock Outputs 28.2.3. PLL Status and Control Signals 28.2.4. System Reset Considerations
28.6. Register Definitions and Bit List x
28.6.1. Status Register 28.6.2. Control Register 28.6.3. Phase Reconfig Control Register
29. DMA Controller Core x
29.1. Core Overview 29.2. Functional Description 29.3. Parameters 29.4. Software Programming Model 29.5. DMA Controller Core Revision History
29.2. Functional Description x
29.2.1. Setting Up DMA Transactions 29.2.2. The Host Read and Write Ports 29.2.3. Addressing and Address Incrementing
29.3. Parameters x
29.3.1. DMA Parameters (Basic) 29.3.2. Advanced Options
29.4. Software Programming Model x
29.4.1. HAL System Library Support 29.4.2. Software Files 29.4.3. Register Map 29.4.4. Interrupt Behavior
30. Modular Scatter-Gather DMA Core x
30.1. Core Overview 30.2. Feature Description 30.3. mSGDMA Interfaces and Parameters 30.4. mSGDMA Descriptors 30.5. Register Map of mSGDMA 30.6. Programming Model 30.7. Modular Scatter-Gather DMA Prefetcher Core 30.8. Driver Implementation 30.9. Example Code Using mSGDMA Core 30.10. Modular Scatter-Gather DMA Core Revision History
30.3. mSGDMA Interfaces and Parameters x
30.3.1. Interface 30.3.2. mSGDMA Parameter Editor
30.3.1. Interface x
30.3.1.1. Descriptor Agent Port 30.3.1.2. Control and Status Register Agent Port 30.3.1.3. Response Port 30.3.1.4. Parameters
30.4. mSGDMA Descriptors x
30.4.1. Read and Write Address Fields 30.4.2. Length Field 30.4.3. Sequence Number Field 30.4.4. Read and Write Burst Count Fields 30.4.5. Read and Write Stride Fields 30.4.6. Control Field
30.5. Register Map of mSGDMA x
30.5.1. Status Register 30.5.2. Control Register 30.5.3. Write Fill Level Register 30.5.4. Read Fill Level Register 30.5.5. Response Fill Level Register 30.5.6. Write Sequence Number Register 30.5.7. Read Sequence Number Register 30.5.8. Component Configuration 1 Register 30.5.9. Component Configuration 2 Register 30.5.10. Component Type Register 30.5.11. Component Version Register
30.6. Programming Model x
30.6.1. Stop DMA Operation 30.6.2. Stop Descriptor Operation 30.6.3. Recovery from Stopped on Error and Stopped on Early Termination
30.7. Modular Scatter-Gather DMA Prefetcher Core x
30.7.1. Functional Description
30.7.1. Functional Description x
30.7.1.1. Supported Features 30.7.1.2. Architecture Overview 30.7.1.3. Descriptor Format 30.7.1.4. Registers 30.7.1.5. Interfaces 30.7.1.6. Software Programming Model 30.7.1.7. Parameters
30.7.1.3. Descriptor Format x
30.7.1.3.1. Descriptor Fields Definition 30.7.1.3.2. Descriptor Processing
30.7.1.4. Registers x
30.7.1.4.1. Register Map 30.7.1.4.2. Control Register 30.7.1.4.3. Descriptor Polling Frequency 30.7.1.4.4. Status
30.7.1.5. Interfaces x
30.7.1.5.1. Avalon® -MM Read Descriptor 30.7.1.5.2. Avalon® -MM Write Descriptor 30.7.1.5.3. Avalon® -MM CSR 30.7.1.5.4. Avalon® -ST Descriptor Source 30.7.1.5.5. Avalon® -ST Response 30.7.1.5.6. IRQ Interface
30.7.1.6. Software Programming Model x
30.7.1.6.1. Setting up Descriptor and mSGDMA Configuration Flow 30.7.1.6.2. Resetting Prefetcher Core Flow
30.8. Driver Implementation x
30.8.1. alt_msgdma_standard_descriptor_async_transfer 30.8.2. alt_msgdma_extended_descriptor_async_transfer 30.8.3. alt_msgdma_descriptor_async_transfer 30.8.4. alt_msgdma_standard_descriptor_sync_transfer 30.8.5. alt_msgdma_extended_descriptor_sync_transfer 30.8.6. alt_msgdma_descriptor_sync_transfer 30.8.7. alt_msgdma_construct_standard_st_to_mm_descriptor 30.8.8. alt_msgdma_construct_standard_mm_to_st_descriptor 30.8.9. alt_msgdma_construct_standard_mm_to_mm_descriptor 30.8.10. alt_msgdma_construct_standard_descriptor 30.8.11. alt_msgdma_construct_extended_st_to_mm_descriptor 30.8.12. alt_msgdma_construct_extended_mm_to_st_descriptor 30.8.13. alt_msgdma_construct_extended_mm_to_mm_descriptor 30.8.14. alt_msgdma_construct_extended_descriptor 30.8.15. alt_msgdma_register_callback 30.8.16. alt_msgdma_open 30.8.17. alt_msgdma_write_standard_descriptor 30.8.18. alt_msgdma_write_extended_descriptor 30.8.19. alt_msgdma_init 30.8.20. alt_msgdma_irq
31. Scatter-Gather DMA Controller Core x
31.1. Core Overview 31.2. Resource Usage and Performance 31.3. Functional Description 31.4. Parameters 31.5. Simulation Considerations 31.6. Software Programming Model 31.7. Programming with SG-DMA Controller 31.8. Scatter-Gather DMA Controller Core Revision History
31.1. Core Overview x
31.1.1. Example Systems 31.1.2. Comparison of SG-DMA Controller Core and DMA Controller Core
31.3. Functional Description x
31.3.1. Functional Blocks and Configurations 31.3.2. DMA Descriptors 31.3.3. Error Conditions
31.6. Software Programming Model x
31.6.1. HAL System Library Support 31.6.2. Software Files 31.6.3. Register Maps 31.6.4. DMA Descriptors 31.6.5. Timeouts
31.7. Programming with SG-DMA Controller x
31.7.1. Data Structure 31.7.2. SG-DMA API 31.7.3. alt_avalon_sgdma_do_async_transfer() 31.7.4. alt_avalon_sgdma_do_sync_transfer() 31.7.5. alt_avalon_sgdma_construct_mem_to_mem_desc() 31.7.6. alt_avalon_sgdma_construct_stream_to_mem_desc() 31.7.7. alt_avalon_sgdma_construct_mem_to_stream_desc() 31.7.8. alt_avalon_sgdma_enable_desc_poll() 31.7.9. alt_avalon_sgdma_disable_desc_poll() 31.7.10. alt_avalon_sgdma_check_descriptor_status() 31.7.11. alt_avalon_sgdma_register_callback() 31.7.12. alt_avalon_sgdma_start() 31.7.13. alt_avalon_sgdma_stop() 31.7.14. alt_avalon_sgdma_open()
32. SDRAM Controller Core x
32.1. Core Overview 32.2. Functional Description 32.3. Configuration 32.4. Hardware Simulation Considerations 32.5. Example Configurations 32.6. Software Programming Model 32.7. Clock, PLL and Timing Considerations 32.8. SDRAM Controller Core Revision History
32.2. Functional Description x
32.2.1. Avalon® memory-mapped interface 32.2.2. Off-Chip SDRAM Interface 32.2.3. Board Layout and Pinout Considerations 32.2.4. Performance Considerations
32.2.2. Off-Chip SDRAM Interface x
32.2.2.1. Signal Timing and Electrical Characteristics 32.2.2.2. Synchronizing Clock and Data Signals 32.2.2.3. Clock Disable Mode Support 32.2.2.4. Sharing Pins with other Avalon® memory-mapped interface Tri-State Devices
32.2.4. Performance Considerations x
32.2.4.1. Open Row Management 32.2.4.2. Sharing Data and Address Pins 32.2.4.3. Hardware Design and Target Device
32.3. Configuration x
32.3.1. Memory Profile Page 32.3.2. Timing Page
32.4. Hardware Simulation Considerations x
32.4.1. SDRAM Controller Simulation Model 32.4.2. SDRAM Memory Model
32.4.2. SDRAM Memory Model x
32.4.2.1. Using the Generic Memory Model 32.4.2.2. Using the SDRAM Manufacturer's Memory Model
32.7. Clock, PLL and Timing Considerations x
32.7.1. Factors Affecting SDRAM Timing 32.7.2. Symptoms of an Untuned PLL 32.7.3. Estimating the Valid Signal Window 32.7.4. Example Calculation
33. Tri-State SDRAM Core x
33.1. Core Overview 33.2. Feature Description 33.3. Configuration Parameter 33.4. Interface 33.5. Reset and Clock Requirements 33.6. Architecture 33.7. Intel SDRAM Tri-State Controller Core Revision History
33.2. Feature Description x
33.2.1. Block Diagram
33.3. Configuration Parameter x
33.3.1. Memory Profile Page 33.3.2. Timing Page
33.6. Architecture x
33.6.1. Avalon® -MM Agent Interface and CSR 33.6.2. Block Level Usage Model
34. Video Sync Generator and Pixel Converter Cores x
34.1. Core Overview 34.2. Video Sync Generator 34.3. Pixel Converter 34.4. Hardware Simulation Considerations 34.5. Video Sync Generator and Pixel Converter Cores Revision History
34.2. Video Sync Generator x
34.2.1. Functional Description 34.2.2. Parameters 34.2.3. Signals 34.2.4. Timing Diagrams
34.3. Pixel Converter x
34.3.1. Functional Description 34.3.2. Parameters 34.3.3. Signals
35. Intel FPGA Interrupt Latency Counter Core x
35.1. Core Overview 35.2. Feature Description 35.3. Component Interface 35.4. Component Parameterization 35.5. Software Access 35.6. Implementation Details 35.7. IP Caveats 35.8. Intel FPGA Interrupt Latency Counter Core Revision History
35.2. Feature Description x
35.2.1. Avalon® -MM Compliant CSR Registers 35.2.2. 32-bit Counter 35.2.3. Interrupt Detector
35.2.1. Avalon® -MM Compliant CSR Registers x
35.2.1.1. Control Register 35.2.1.2. Frequency Register 35.2.1.3. Counter Stop Registers 35.2.1.4. Latency Data Registers 35.2.1.5. Data Valid Registers 35.2.1.6. IRQ Active Registers
35.5. Software Access x
35.5.1. Routine for Level Sensitive Interrupts 35.5.2. Routine for Edge/Pulse Sensitive Interrupts
35.6. Implementation Details x
35.6.1. Interrupt Latency Counter Architecture
36. Performance Counter Unit Core x
36.1. Core Overview 36.2. Functional Description 36.3. Configuration 36.4. Hardware Simulation Considerations 36.5. Software Programming Model 36.6. Performance Counter API 36.7. Performance Counter Core Revision History
36.2. Functional Description x
36.2.1. Section Counters 36.2.2. Global Counter 36.2.3. Register Map 36.2.4. System Reset
36.3. Configuration x
36.3.1. Define Counters 36.3.2. Multiple Clock Domain Considerations
36.5. Software Programming Model x
36.5.1. Software Files 36.5.2. Using the Performance Counter 36.5.3. Interrupt Behavior
36.6. Performance Counter API x
36.6.1. PERF_RESET() 36.6.2. PERF_START_MEASURING() 36.6.3. PERF_STOP_MEASURING() 36.6.4. PERF_BEGIN() 36.6.5. PERF_END() 36.6.6. perf_print_formatted_report() 36.6.7. perf_get_total_time() 36.6.8. perf_get_section_time() 36.6.9. perf_get_num_starts() 36.6.10. alt_get_cpu_freq()
37. Vectored Interrupt Controller Core x
37.1. Core Overview 37.2. Functional Description 37.3. Register Maps 37.4. Parameters 37.5. Intel FPGA HAL Software Programming Model 37.6. Implementing the VIC in Platform Designer 37.7. Example Designs 37.8. Advanced Topics 37.9. Vectored Interrupt Controller Core Revision History
37.2. Functional Description x
37.2.1. External Interfaces 37.2.2. Functional Blocks 37.2.3. Daisy Chaining VIC Cores 37.2.4. Latency Information
37.2.1. External Interfaces x
37.2.1.1. clk 37.2.1.2. irq_input 37.2.1.3. interrupt_controller_out 37.2.1.4. interrupt_controller_in 37.2.1.5. csr_access
37.2.2. Functional Blocks x
37.2.2.1. Interrupt Request Block 37.2.2.2. Priority Processing Block 37.2.2.3. Vector Generation Block
37.5. Intel FPGA HAL Software Programming Model x
37.5.1. Software Files 37.5.2. Macros 37.5.3. Data Structure 37.5.4. VIC API 37.5.5. Run-time Initialization 37.5.6. Board Support Package
37.5.4. VIC API x
37.5.4.1. alt_vic_sw_interrupt_set() 37.5.4.2. alt_vic_sw_interrupt_clear() 37.5.4.3. alt_vic_sw_interrupt_status() 37.5.4.4. alt_vic_irq_set_level()
37.5.6. Board Support Package x
37.5.6.1. altera_vic_driver.enable_preemption 37.5.6.2. altera_vic_driver.enable_preemption_into_new_register_set 37.5.6.3. altera_vic_driver.enable_preemption_rs_<n> 37.5.6.4. altera_vic_driver.linker_section 37.5.6.5. altera_vic_driver.<name>.vec_size 37.5.6.6. altera_vic_driver.<name>.irq<n>_rrs 37.5.6.7. altera_vic_driver.<name>.irq<n>_ril 37.5.6.8. altera_vic_driver.<name>.irq<n>_rnmi 37.5.6.9. Default Settings for RRS and RIL 37.5.6.10. VIC BSP Design Rules for Intel FPGA HAL Implementation 37.5.6.11. RTOS Considerations
37.6. Implementing the VIC in Platform Designer x
37.6.1. Adding VIC Hardware 37.6.2. Software for VIC
37.6.1. Adding VIC Hardware x
37.6.1.1. Adding the EIC Interface Shadow Register Set 37.6.1.2. VIC Instantiation, Parameterization, and Connection
37.6.1.2. VIC Instantiation, Parameterization, and Connection x
37.6.1.2.1. Instantiation 37.6.1.2.2. Parameterization 37.6.1.2.3. VIC Connections
37.6.2. Software for VIC x
37.6.2.1. alt_ic_isr_register() versus alt_irq_register()
37.7. Example Designs x
37.7.1. Example Description 37.7.2. Example Usage 37.7.3. Software Description 37.7.4. Positioning the ISR in Vector Table 37.7.5. Latency Measurement with the Performance Counter
37.7.4. Positioning the ISR in Vector Table x
37.7.4.1. Increase the Vector Table Entry Size 37.7.4.2. Do Not Register the ISR 37.7.4.3. Insert ISR in Vector Table
37.8. Advanced Topics x
37.8.1. Real Time Latency Concerns 37.8.2. Software Interrupt
37.8.1. Real Time Latency Concerns x
37.8.1.1. Pipeline Latency 37.8.1.2. Cause Latency 37.8.1.3. Selection Latency 37.8.1.4. Funnel Latency 37.8.1.5. Compiler-Related Latency
38. Avalon® -ST Data Pattern Generator and Checker Cores x
38.1. Core Overview 38.2. Data Pattern Generator 38.3. Data Pattern Checker 38.4. Hardware Simulation Considerations 38.5. Software Programming Model 38.6. Avalon® -ST Data Pattern Generator and Checker Cores Revision History
38.2. Data Pattern Generator x
38.2.1. Functional Description 38.2.2. Configuration
38.3. Data Pattern Checker x
38.3.1. Functional Description 38.3.2. Configuration
38.5. Software Programming Model x
38.5.1. Register Maps
39. Avalon® -ST Test Pattern Generator and Checker Cores x
39.1. Core Overview 39.2. Resource Utilization and Performance 39.3. Test Pattern Generator 39.4. Test Pattern Checker 39.5. Hardware Simulation Considerations 39.6. Software Programming Model 39.7. Test Pattern Generator API 39.8. Test Pattern Checker API 39.9. Avalon® -ST Test Pattern Generator and Checker Cores Revision History
39.3. Test Pattern Generator x
39.3.1. Functional Description 39.3.2. Configuration
39.4. Test Pattern Checker x
39.4.1. Functional Description 39.4.2. Configuration
39.6. Software Programming Model x
39.6.1. HAL System Library Support 39.6.2. Software Files 39.6.3. Register Maps
39.7. Test Pattern Generator API x
39.7.1. data_source_reset() 39.7.2. data_source_init() 39.7.3. data_source_get_id() 39.7.4. data_source_get_supports_packets() 39.7.5. data_source_get_num_channels() 39.7.6. data_source_get_symbols_per_cycle() 39.7.7. data_source_set_enable() 39.7.8. data_source_get_enable() 39.7.9. data_source_set_throttle() 39.7.10. data_source_get_throttle() 39.7.11. data_source_is_busy() 39.7.12. data_source_fill_level() 39.7.13. data_source_send_data()
39.8. Test Pattern Checker API x
39.8.1. data_sink_reset() 39.8.2. data_sink_init() 39.8.3. data_sink_get_id() 39.8.4. data_sink_get_supports_packets() 39.8.5. data_sink_get_num_channels() 39.8.6. data_sink_get_symbols_per_cycle() 39.8.7. data_sink_set enable() 39.8.8. data_sink_get_enable() 39.8.9. data_sink_set_throttle() 39.8.10. data_sink_get_throttle() 39.8.11. data_sink_get_packet_count() 39.8.12. data_sink_get_symbol_count() 39.8.13. data_sink_get_error_count() 39.8.14. data_sink_get_exception() 39.8.15. data_sink_exception_is_exception() 39.8.16. data_sink_exception_has_data_error() 39.8.17. data_sink_exception_has_missing_sop() 39.8.18. data_sink_exception_has_missing_eop() 39.8.19. data_sink_exception_signalled_error() 39.8.20. data_sink_exception_channel()
40. System ID Peripheral Core x
40.1. Core Overview 40.2. Functional Description 40.3. Configuration 40.4. Software Programming Model 40.5. System ID Core Revision History
40.4. Software Programming Model x
40.4.1. alt_avalon_sysid_test()
41. Avalon® Packets to Transactions Converter Core x
41.1. Core Overview 41.2. Functional Description 41.3. Avalon® Packets to Transactions Converter Core Revision History
41.2. Functional Description x
41.2.1. Interfaces 41.2.2. Operation
42. Avalon® -ST Multiplexer and Demultiplexer Cores x
42.1. Core Overview 42.2. Multiplexer 42.3. Demultiplexer 42.4. Hardware Simulation Considerations 42.5. Software Programming Model 42.6. Avalon® -ST Multiplexer and Demultiplexer Cores Revision History
42.1. Core Overview x
42.1.1. Resource Usage and Performance
42.2. Multiplexer x
42.2.1. Functional Description 42.2.2. Parameters
42.3. Demultiplexer x
42.3.1. Functional Description 42.3.2. Parameters
43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP x
43.1. Core Overview 43.2. Functional Description 43.3. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores Revision History
43.2. Functional Description x
43.2.1. Interfaces— Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 43.2.2. Operation— Avalon® -ST Bytes to Packets Converter IP 43.2.3. Operation— Avalon® -ST Packets to Bytes Converter IP
44. Avalon® -ST Delay Core x
44.1. Core Overview 44.2. Functional Description 44.3. Parameters 44.4. Avalon® -ST Delay Core Revision History
44.2. Functional Description x
44.2.1. Reset 44.2.2. Interfaces
45. Avalon® -ST Round Robin Scheduler Core x
45.1. Core Overview 45.2. Performance and Resource Utilization 45.3. Functional Description 45.4. Parameters 45.5. Avalon® -ST Round Robin Scheduler Core Revision History
45.3. Functional Description x
45.3.1. Interfaces 45.3.2. Operations
46. Avalon® -ST Splitter Core x
46.1. Core Overview 46.2. Functional Description 46.3. Parameters 46.4. Avalon® -ST Splitter Core Revision History
46.2. Functional Description x
46.2.1. Backpressure 46.2.2. Interfaces
47. Avalon® -MM DDR Memory Half Rate Bridge Core x
47.1. Core Overview 47.2. Resource Usage and Performance 47.3. Functional Description 47.4. Instantiating the Core in Platform Designer 47.5. Example System 47.6. Avalon® -MM DDR Memory Half Rate Bridge Core Revision History
48. Intel FPGA GMII to RGMII Converter Core x
48.1. Core Overview 48.2. Feature Description 48.3. Parameters 48.4. Intel FPGA GMII to RGMII Converter Core Interface 48.5. Functional Description 48.6. Intel FPGA HPS EMAC Interface Splitter Core 48.7. Intel FPGA GMII to RGMII Converter Core Revision History
48.2. Feature Description x
48.2.1. Supported Features 48.2.2. Unsupported Features
48.3. Parameters x
48.3.1. IP Configuration Parameter
48.5. Functional Description x
48.5.1. Architecture
48.5.1. Architecture x
48.5.1.1. Data Path 48.5.1.2. Clock Scheme
48.5.1.2. Clock Scheme x
48.5.1.2.1. Transmit 48.5.1.2.2. Receive
48.6. Intel FPGA HPS EMAC Interface Splitter Core x
48.6.1. Parameter
48.6.1. Parameter x
48.6.1.1. System Info Parameter 48.6.1.2. HDL Parameter 48.6.1.3. Interface Signals 48.6.1.4. Register 48.6.1.5. Avalon® -MM Agent Interface
48.6.1.4. Register x
48.6.1.4.1. Register Memory Map 48.6.1.4.2. Register Description
49. HPS GMII to RGMII Adapter Intel® FPGA IP x
49.1. Core Overview 49.2. Feature Description 49.3. Parameters 49.4. HPS GMII to RGMII Adapter Intel® FPGA IP Interface 49.5. Functional Description 49.6. HPS GMII to RGMII Adapter Intel® FPGA IP Revision History
49.2. Feature Description x
49.2.1. Supported Features 49.2.2. Unsupported Features
49.3. Parameters x
49.3.1. IP Configuration Parameter
49.5. Functional Description x
49.5.1. Architecture
49.5.1. Architecture x
49.5.1.1. Data Path 49.5.1.2. Clock Scheme
49.5.1.2. Clock Scheme x
49.5.1.2.1. Transmit 49.5.1.2.2. Receive
50. Intel FPGA MII to RMII Converter Core x
50.1. Supported Features 50.2. Interface Signals 50.3. Parameters 50.4. Functional Description 50.5. Intel FPGA MII to RMII Converter Core Revision History
50.4. Functional Description x
50.4.1. Clocking Scheme 50.4.2. Transmit Interface 50.4.3. Receive Interface
51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP x
51.1. Core Overview 51.2. Feature Description 51.3. Core Architecture 51.4. Configuration Parameters 51.5. Interface 51.6. Registers 51.7. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Intel® FPGA IP Core Revision History
51.2. Feature Description x
51.2.1. Supported Features
51.3. Core Architecture x
51.3.1. Data Path 51.3.2. Clock Scheme 51.3.3. MAC Speed 51.3.4. Transmit Elastic Buffer 51.3.5. Avalon® Memory-Mapped Interface Agent Interface 51.3.6. Programming Model
51.3.4. Transmit Elastic Buffer x
51.3.4.1. GMII to MII Mode Transition
51.6. Registers x
51.6.1. Register Memory Map 51.6.2. Register Description
52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core x
52.1. Supported Features 52.2. Functional Description 52.3. Interface Signals 52.4. Register Memory Map and Description 52.5. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core Revision History
53. Intel FPGA MSI to GIC Generator Core x
53.1. Core Overview 53.2. Background 53.3. Feature Description 53.4. Intel FPGA MSI to GIC Generator Core Revision History
53.3. Feature Description x
53.3.1. Interrupt Servicing Process 53.3.2. Registers of Component 53.3.3. Unsupported Feature
53.3.2. Registers of Component x
53.3.2.1. Status Register 53.3.2.2. Error Register 53.3.2.3. Interrupt Mask Register
54. Cache Coherency Translator Intel® FPGA IP x
54.1. Core Overview 54.2. IP Parameters 54.3. Use Case 54.4. Functional Description 54.5. Interface Signals 54.6. Clocking 54.7. Reset 54.8. Clock and Reset Signals 54.9. Register Description 54.10. Cache Coherency Translator Intel® FPGA IP Revision History
54.4. Functional Description x
54.4.1. Fixed Value 54.4.2. GPIO Mode 54.4.3. CSR Mode
55. Altera ACE5-Lite Cache Coherency Translator x
55.1. Core Overview 55.2. IP Parameters 55.3. Use Case 55.4. Functional Description 55.5. Interface Signals 55.6. Clocking 55.7. Reset 55.8. Clock and Reset Signals 55.9. Register Description 55.10. Altera ACE5-Lite Cache Coherency Translator Revision History
56. Lightweight UART Core x
56.1. Core Overview 56.2. Functional Description 56.3. Configuration Parameters 56.4. Instantiating the Core 56.5. Software Programming Model 56.6. Lightweight UART Core Revision History
56.2. Functional Description x
56.2.1. Avalon® Memory-Mapped Agent Interface and Registers 56.2.2. RS-232 Interface 56.2.3. Transistor-Transistor Logic (TTL) Interface 56.2.4. Handshaking Signal (CTS/RTS Flow Control) 56.2.5. Transmitter Logic 56.2.6. Receiver Logic 56.2.7. Baud Rate Generation
56.3. Configuration Parameters x
56.3.1. Implement TXFIFO and RXFIFO in Register 56.3.2. Depth of TXFIFO and RXFIFO 56.3.3. Remaining RXFIFO Depth to Assert Almost Full 56.3.4. Include CTS/RTS
56.4. Instantiating the Core x
56.4.1. Baud Rate Options 56.4.2. Baud Rate (bps) Setting 56.4.3. Baud Rate Can Be Changed by Software Setting 56.4.4. Data Bits, Stop Bits, Parity 56.4.5. Synchronizer Stages 56.4.6. Streaming Data (DMA) Control
56.4.6. Streaming Data (DMA) Control x
56.4.6.1. Include End-of-Packet Register
56.5. Software Programming Model x
56.5.1. HAL System Library Support 56.5.2. Software Files 56.5.3. Supported Features 56.5.4. Register Map 56.5.5. Interrupt Behavior
56.5.1. HAL System Library Support x
56.5.1.1. Driver Options: Fast vs. Small Implementations 56.5.1.2. ioctl() Operations
56.5.1.1. Driver Options: Fast vs. Small Implementations x
56.5.1.1.1. UART API 56.5.1.1.2. UART Device Structure
56.5.4. Register Map x
56.5.4.1. Transmit Data FIFO (TXFIFO) 56.5.4.2. Receive data FIFO (RXFIFO) 56.5.4.3. Status Register 56.5.4.4. Control Register 56.5.4.5. Divisor Register 56.5.4.6. Endofpacket Register 56.5.4.7. RXFIFO Level Register (RXFIFO_LVL) 56.5.4.8. TXFIFO level register (TXFIFO_LVL)
1. Introduction
2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores
3. Avalon® -ST Serial Peripheral Interface Core
4. SPI Core
5. SPI Agent/JTAG to Avalon® Host Bridge Cores
6. Intel eSPI Agent Core
7. eSPI to LPC Bridge Core
8. Ethernet MDIO Core
9. Intel FPGA 16550 Compatible UART Core
10. UART Core
11. JTAG UART Core
12. Intel FPGA Avalon® Mailbox Core
13. Intel FPGA Avalon® Mutex Core
14. Intel FPGA Avalon® I2C (Host) Core
15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core
16. Intel FPGA Avalon® Compact Flash Core
17. EPCS/EPCQA Serial Flash Controller Core
18. Intel FPGA Serial Flash Controller Core
19. Intel FPGA Serial Flash Controller II Core
20. Intel FPGA Generic QUAD SPI Controller Core
21. Intel FPGA Generic QUAD SPI Controller II Core
22. Interval Timer Core
23. Intel FPGA Avalon FIFO Memory Core
24. On-Chip Memory (RAM and ROM) Intel FPGA IP
25. On-Chip Memory II (RAM or ROM) Intel FPGA IP
26. Optrex 16207 LCD Controller Core
27. PIO Core
28. PLL Cores
29. DMA Controller Core
30. Modular Scatter-Gather DMA Core
31. Scatter-Gather DMA Controller Core
32. SDRAM Controller Core
33. Tri-State SDRAM Core
34. Video Sync Generator and Pixel Converter Cores
35. Intel FPGA Interrupt Latency Counter Core
36. Performance Counter Unit Core
37. Vectored Interrupt Controller Core
38. Avalon® -ST Data Pattern Generator and Checker Cores
39. Avalon® -ST Test Pattern Generator and Checker Cores
40. System ID Peripheral Core
41. Avalon® Packets to Transactions Converter Core
42. Avalon® -ST Multiplexer and Demultiplexer Cores
43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP
44. Avalon® -ST Delay Core
45. Avalon® -ST Round Robin Scheduler Core
46. Avalon® -ST Splitter Core
47. Avalon® -MM DDR Memory Half Rate Bridge Core
48. Intel FPGA GMII to RGMII Converter Core
49. HPS GMII to RGMII Adapter Intel® FPGA IP
50. Intel FPGA MII to RMII Converter Core
51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP
52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core
53. Intel FPGA MSI to GIC Generator Core
54. Cache Coherency Translator Intel® FPGA IP
55. Altera ACE5-Lite Cache Coherency Translator
56. Lightweight UART Core

32.7.4. Example Calculation

This section demonstrates a calculation of the signal window for a Micron MT48LC4M32B2-7 SDRAM chip and design targeting the Stratix®  II EP2S60F672C5 device. This example uses a CAS latency (CL) of 3 cycles, and a clock frequency of 50 MHz. All SDRAM signals on the device are registered in I/O cells, enabled with the Fast Input Register and Fast Output Register logic options in the Quartus® Prime software.
Table 365.  Timing Parameters for Micron MT48LC4M32B2 SDRAM Device
Parameter Symbol Value (ns) in -7 Speed Grade
Min. Max.
Access time from CLK (pos. edge) CL = 3 tAC(3) — 5.5
CL = 2 tAC(2) — 8
CL = 1 tAC(1) — 17
Address hold time tAH 1 —
Address setup time tAS 2 —
CLK high-level width tCH 2.75 —
CLK low-level width tCL 2.75 —
Clock cycle time CL = 3 tCK(3) 7 —
CL = 2 tCK(2) 10 —
CL = 1 tCK(1) 20 —
CKE hold time tCKH 1 —
CKE setup time tCKS 2 —
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 —
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2 —
Data-in hold time tDH 1  
Data-in setup time tDS 2  
Data-out high-impedance time CL = 3 tHZ(3)   5.5
CL = 2 tHZ(2) — 8
CL = 1 tHZ(1) — 17
Data-out low-impedance time tLZ 1 —
Data-out hold time tOH 2.5  

The FPGA I/O Timing Parameters table below shows the relevant timing information, obtained from the Timing Analyzer section of the Quartus® Prime Compilation Report. The values in the table are the maximum or minimum values among all device pins related to the SDRAM. The variance in timing between the SDRAM pins on the device is small (less than 100 ps) because the registers for these signals are placed in the I/O cell.

Table 366.  FPGA I/O Timing Parameters
Parameter Symbol Value (ns)
Clock period tCLK 20
Minimum clock-to-output time tCO_MIN 2.399
Maximum clock-to-output time tCO_MAX 2.477
Maximum hold time after clock tH_MAX –5.607
Maximum setup time before clock tSU_MAX 5.936

You must compile the design in the Quartus® Prime software to obtain the I/O timing information for the design. Although Intel FPGA device family datasheets contain generic I/O timing information for each device, the Quartus® Prime Compilation Report provides the most precise timing information for your specific design.

The timing values found in the compilation report can change, depending on fitting, pin location, and other Quartus® Prime logic settings. When you recompile the design in the Quartus® Prime software, verify that the I/O timing has not changed significantly.

The following examples illustrate the calculations from figures Maximum SDRAM Clock Lag and Maximum Lead also using the values from the Timing Parameters and FPGA I/O Timing Parameters table.

The SDRAM clock can lag the controller clock by the lesser of Read Lag or Write Lag:

Read Lag = tOH(SDRAM) – tH_MAX(FPGA)

= 2.5 ns – (–5.607 ns) = 8.107 ns

or

Write Lag = tCLK – tCO_MAX(FPGA) – tDS(SDRAM)

= 20 ns – 2.477 ns – 2 ns = 15.523 ns

The SDRAM clock can lead the controller clock by the lesser of Read Lead or Write Lead:

Read Lead = tCO_MIN(FPGA) – tDH(SDRAM)

= 2.399 ns – 1.0 ns = 1.399 ns

or

Write Lead = tCLK – tHZ(3)(SDRAM) – tSU_MAX(FPGA)

= 20 ns – 5.5 ns – 5.936 ns = 8.564 ns

Therefore, for this example you can shift the phase of the SDRAM clock from –8.107 ns to 1.399 ns relative to the controller clock. Choosing a phase shift in the middle of this window results in the value (–8.107 + 1.399)/2 = –3.35 ns.

Level Two Title