Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

23.2.3. Avalon® -MM Write Agent to Avalon® -ST Source

In this configuration, the input is an Avalon® -MM write agent with a width of 32 bits as shown in the FIFO with Avalon® -MM Input Interface and Avalon® -ST Output Interface figure below. The Avalon® -ST output (source) data width must also be 32 bits. You can configure output interface parameters, including: bits per symbol, symbols per beat, and the width of the channel and error signals. The FIFO core performs the endian conversion to conform to the output interface protocol.

The signals that comprise the output interface are mapped into bits in the Avalon® address space. If Allow backpressure is turned on, the input interface asserts waitrequest to indicate that the FIFO core does not have enough space for the transaction to complete.

Figure 74. FIFO with Avalon® -MM Input Interface and Avalon® -ST Output Interface
Table 259.  Bit Field
Offset 31         24 23   19 18     16 15     13 12     8 7     4 3 2 1 0
base + 0 Symbol 3 Symbol 2 Symbol 1 Symbol 0
base + 1 reserved reserved error reserved channel reserved empty EOP SOP
Table 260.  Memory Map
Offset Bits Field Description
0 31:0 SYMBOL_0, SYMBOL_1, SYMBOL_2 .. SYMBOL_n Packet data. The value of the Symbols per beat parameter specifies the number of fields in this register; Bits per symbol specifies the width of each field.
1 0 SOP The value of the startofpacket signal.
1 EOP The value of the endofpacket signal.
6:2 EMPTY The value of the empty signal.
7 Reserved.
15:8 CHANNEL The value of the channel signal. The number of bits occupied corresponds to the width of the signal. For example, if the width of the channel signal is 5, bits 8 to 12 are occupied and bits 13 to 15 are unused.
23:16 ERROR The value of the error signal. The number of bits occupied corresponds to the width of the signal. For example, if the width of the error signal is 3, bits 16 to 18 are occupied and bits 19 to 23 are unused.
31:24 Reserved.

If Enable packet data is turned off, the Avalon® -MM write host writes all data at address offset 0 repeatedly to push data into the FIFO core.

If Enable packet data is turned on, the Avalon® -MM write host starts by writing the SOP, ERROR (optional), CHANNEL (optional), EOP, and EMPTY packet status information at address offset 1. Writing to address offset 1 does not push data into the FIFO core. The Avalon® -MM host then writes packet data to address offset 0 repeatedly, pushing 8-bit symbols into the FIFO core. Whenever a valid write occurs at address offset 0, the data and its respective packet information is pushed into the FIFO core. Subsequent data is written at address offset 0 without the need to clear the SOP field. Rewriting to address offset 1 is not required each time if the subsequent data to be pushed into the FIFO core is not the end-of-packet data, as long as ERROR and CHANNEL do not change.

At the end of each packet, the Avalon® -MM host writes to the address at offset 1 to set the EOP bit to 1, before writing the last symbol of the packet at offset 0. The write host uses the empty field to indicate the number of unused symbols at the end of the transfer. If the last packet data is not aligned with the symbols per beat, the EMPTY field indicates the number of empty symbols in the last packet data. For example, if the Avalon® -ST interface has symbols per beat of 4, and the last packet only has 3 symbols, the empty field will be 1, indicating that one symbol (the least significant symbol in the memory map) is empty.