Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

14.7.6. Programming Model

The following flowchart illustrates the recommended programming flow for the core.

Figure 53. Programming Model Flowchart
Note: When either ARBLOST_DET or NACK_DET occur, you need to clear its respective interrupt status register bits in their error handling procedure before continuing with a new I2C transfer. A new I2C transfer can be initiated with or without disabling the core.

Illustration: How to use the API

int main() 
{
  ALT_AVALON_I2C_DEV_t *i2c_dev;  //pointer to instance structure
  alt_u8 txbuffer[0x200];
  alt_u8 rxbuffer[0x200];  
  int i;
  ALT_AVALON_I2C_STATUS_CODE status;
  
  //get a pointer to the avalon i2c instance
  i2c_dev = alt_avalon_i2c_open("/dev/i2c_0");
  if (NULL==i2c_dev)
  {
      printf("Error: Cannot find /dev/i2c_0\n");
      return 1;
  }
  
  //set the address of the device using 
  
  alt_avalon_i2c_master_target_set(i2c_dev,0x51)	

  //write data to an eeprom at address 0x0200
  
  txbuffer[0]=2; txbuffer[1]=0;  
  
  //The eeprom address which will be sent as first two bytes of data
  
  for (i=0;i<0x10;i++) txbuffer[i+2]=i;   //some data to write
  status=alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 0x10+2, ALT_AVALON_I2C_NO_INTERRUPTS);
  if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL

  //read back the data into rxbuffer
  //This command sends the 2 byte eeprom data address required by the eeprom
  //Then does a restart and receives the data.
  status=alt_avalon_i2c_master_tx_rx(i2c_dev, txbuffer, 2, rxbuffer, 0x10, ALT_AVALON_I2C_NO_INTERRUPTS);
  if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL
  return 0;
}

//Using the optional irq callback:

int main() 
{
  ALT_AVALON_I2C_DEV_t *i2c_dev;  //pointer to instance structure
  alt_u8 txbuffer[0x210];
  alt_u8 rxbuffer[0x200];  
  int i;
  ALT_AVALON_I2C_STATUS_CODE status;

  //storage for the optional provided interrupt handler structure 
  IRQ_DATA_t irq_data;
  
  //get a pointer to the avalon i2c instance
  i2c_dev = alt_avalon_i2c_open("/dev/i2c_0");
  if (NULL==i2c_dev)
  {
      printf("Error: Cannot find /dev/i2c_0\n");
      return 1;
  }
  
  //register the optional interrupt callback.  
  alt_avalon_i2c_register_optional_irq_handler(i2c_dev,&irq_data);

  //set the address of the device we will be using
  alt_avalon_i2c_master_target_set(i2c_dev,0x51);	 

  //assume an eeprom at address 0x51

  //write data to an eeprom at address (within the eeprom) 0x0200
  txbuffer[0]=2; 
  txbuffer[1]=0;  
  
  //The eeprom data address which will be sent as first two bytes of data

  for (i=0;i<0x10;i++) txbuffer[i+2]=i;   //some data to write

  while (1) {  //for function retry
     status=alt_avalon_i2c_master_tx(i2c_dev, txbuffer, 0x10+2, ALT_AVALON_I2C_USE_INTERRUPTS);
     
     
     if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL

     //Completion should be checked by using the alt_avalon_i2c_interrupt_transaction_status function.
     //Note: Interrupt and non-interrupt transactions can be mixed in any sequence, so if desired this short address setup transaction can use ALT_AVALON_I2C_NO_INTERRUPTS.
     
     
     while (alt_avalon_i2c_interrupt_transaction_status(i2c_dev) == ALT_AVALON_I2C_BUSY) {  }
    
     //Did the transaction complete OK? If yes then break out of this retry loop, otherwise, have to do the transaction again
     //You may want to have a retry limit instead of 
     
     while (1)
     if (alt_avalon_i2c_interrupt_transaction_status(i2c_dev) == ALT_AVALON_I2C_SUCCESS) break;
  }
  while (1) { 
      
     //for function retry, read back the data into rxbuffer
     
     
     status=alt_avalon_i2c_master_tx_rx(i2c_dev, txbuffer, 2, rxbuffer, 0x10, ALT_AVALON_I2C_USE_INTERRUPTS);
     
     
     if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL
  
     //For this example we will just waste the time in a loop.
     
     
     while (alt_avalon_i2c_interrupt_transaction_status(i2c_dev) == ALT_AVALON_I2C_BUSY) {  }
    
     //Did the transaction complete OK
     
     if (alt_avalon_i2c_interrupt_transaction_status(i2c_dev) == ALT_AVALON_I2C_SUCCESS) break;
  }
  
  return 0;
}