Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

23.3.1. FIFO Settings

The following sections outline the settings that pertain to the FIFO core as a whole.

Depth

Depth indicates the depth of the FIFO buffer, in Avalon® -ST bits or Avalon® -MM words. The default depth is 16. When dual clock mode is used, the actual FIFO depth is equal to depth-3. This is due to clock crossing and to avoid FIFO overflow.

Clock Settings

The two options are Single clock mode and Dual clock mode. In Single clock mode, all interface ports use the same clock. In Dual clock mode, input data and input side status are on the input clock domain. Output data and output side status are on the output clock domain.

Status Port

The optional status ports are Avalon® -MM agents. To include the optional input side status interface, turn on Create status interface for input on the Platform Designer MegaWizard. For FIFOs whose input and output ports operate in separate clock domains, you can include a second status interface by turning on Create status interface for output. Turning on Enable IRQ for status ports adds an interrupt signal to the status ports.

FIFO Implementation

This option determines if the FIFO core is built from registers or embedded memory blocks. The default is to construct the FIFO core from embedded memory blocks.