Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

7.4.1. FIFO Implementation

All FIFOs are used in peripheral channel to buffer up the incoming transactions. When the eSPI-to-LPC bridge is busy transferring data down the LPC interface, the transactions from the eSPI host are stored using the PC_RXFIFO or NP_RXFIFO until the bridge is idle. The PC_RXFIFO stores posted transactions while the NP_RXFIFO stores non-posted transactions.

The RXFIFOs can store more than one eSPI transaction (command byte, header byte and write data byte) until it is full. When the FIFO depth is less than MAX_PC_PAYLOAD_SIZE + 1 complete header + 1 command byte or 1 complete header + 1 command byte for NP_RXFIFO , the PC_FREE/NP_FREE status register bit is de-asserted.

The Pre_RXFIFO stores an incoming eSPI transaction for CRC error checking purposes. CRC error check is performed after pushing the last byte of a eSPI transaction into Pre_RXFIFO. If CRC error is high, then the eSPI transaction is dropped to avoid translation into a LPC transaction. If CRC error is low, the eSPI transaction is pushed into NP_RXFIFO or PC_RXFIFO for translating into a LPC transaction.

The PC_TXFIFO stores response transaction from the downstream LPC devices. The PC_ AVAIL status register bit goes high only when a complete response transaction is stored in the PC_TXFIFO.

The Pre_TXFIFO stores an incoming LPC transaction for error checking purposes. In the event of LPC transaction abort or LPC transaction sync error, the transaction is dropped from the Pre_TXFIFO. The transaction is pushed into PC_TXFIFO provided that there is no error, then to eSPI host.

All the FIFOs are 8-bit wide. The figure below shows the content of the RXFIFO which can store one complete eSPI transaction.
Figure 26. RXFIFO Contents