Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

30.4.6. Control Field

The control field is available for both the standard and extended descriptor formats. This field can be programmed to configure parked descriptors, error handling, and interrupt masks. The interrupt masks are programmed into the descriptor so that interrupt enables are unique for each transfer.

Table 308.  Descriptor Control Field Bit Definition
Bit Sub-Field Name Definition
31

Go

Commits all the descriptor information into the descriptor FIFO.

As the host writes different fields in the descriptor, FIFO byte enables are asserted to transfer the write data to appropriate byte locations in the FIFO.

However, the data written is not committed until the go bit has been written.

As a result, ensure that the go bit is the last bit written for each descriptor.

Writing '1' to the go bit commits the entire descriptor into the descriptor FIFO(s).

30:26 <reserved>  
25 Wait for write responses When set, on completion of the DMA transfer, the host is only notified when all the outstanding writes have been responded. Those outstanding writes include writes transfer initiated by previous descriptor.

This field is valid only when Enable Write Response parameter is set. Enabling this bit resulted in longer time for write response host to move into the next descriptor. Therefore, it is recommended to set this field on the last descriptor of the transfer.

24 Early done enable

Hides the latency between read descriptors.

When the read host is set, it does not wait for pending reads to return before requesting another descriptor.

Typically this bit is set for all descriptors except the last one. This bit is most effective for hiding high read latency. For example, it reads from SDRAM, PCIe, and SRIO.

23:16 Transmit Error / Error IRQ Enable

For for Avalon® -MM to Avalon® -ST transfers, this field is used to specify a transmit error.

This field is commonly used for transmitting error information downstream to streaming components, such as an Ethernet MAC.

In this mode, these control bits control the error bits on the streaming output of the read host.

For Avalon® -ST to Avalon® -MM transfers, this field is used as an error interrupt mask.

As errors arrive at the write host streaming sink port, they are held persistently. When the transfer completes, if any error bits were set at any time during the transfer and the error interrupt mask bits are set, then the host receives an interrupt.

In this mode, these control bits are used as an error encountered interrupt enable.

15 Early Termination IRQ Enable

Signals an interrupt to the host when a Avalon® -ST to Avalon® -MM transfer completes early.

For example, if you set this bit and set the length field to 1MB for Avalon® -ST to Avalon® -MM transfers, this interrupt asserts when more than 1MB of data arrives to the write host without the end of packet being seen.

14 Transfer Complete IRQ Enable

Signals an interrupt to the host when a transfer completes.

In the case of Avalon® -MM to Avalon® -ST transfers, this interrupt is based on the read host completing a transfer.

In the case of Avalon® -ST to Avalon® -MM or Avalon® -MM to Avalon® -MM transfers, this interrupt is based on the write host completing a transfer.

13 <reserved>  
12 End on EOP

End on end of packet allows the write host to continuously transfer data during Avalon® -ST to Avalon® -MM transfers without knowing how much data is arriving ahead of time.

This bit is commonly set for packet-based traffic such as Ethernet.

11 Park Writes When set, the dispatcher continues to reissue the same descriptor to the write host when no other descriptors are buffered.
10 Park Reads When set, the dispatcher continues to reissue the same descriptor to the read host when no other descriptors are buffered. This is commonly used for video frame buffering.
9 Generate EOP Emits an end of packet on last beat of a Avalon® -MM to Avlaon-ST transfer
8 Generate SOP Emits a start of packet on the first beat of a Avalon® -MM to Avalon® -ST transfer
7:0 Transmit Channel Emits a channel number during Avalon® -MM to Avalon® -ST transfers