Embedded Peripherals IP User Guide

ID 683130
Date 8/11/2025
Public
Document Table of Contents
1. Introduction 2. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 3. Avalon® -ST Serial Peripheral Interface Core 4. SPI Core 5. SPI Agent/JTAG to Avalon® Host Bridge Cores 6. Intel eSPI Agent Core 7. eSPI to LPC Bridge Core 8. Ethernet MDIO Core 9. Intel FPGA 16550 Compatible UART Core 10. UART Core 11. JTAG UART Core 12. Intel FPGA Avalon® Mailbox Core 13. Intel FPGA Avalon® Mutex Core 14. Intel FPGA Avalon® I2C (Host) Core 15. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 16. Intel FPGA Avalon® Compact Flash Core 17. EPCS/EPCQA Serial Flash Controller Core 18. Intel FPGA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller II Core 20. Intel FPGA Generic QUAD SPI Controller Core 21. Intel FPGA Generic QUAD SPI Controller II Core 22. Interval Timer Core 23. Intel FPGA Avalon FIFO Memory Core 24. On-Chip Memory (RAM and ROM) Intel FPGA IP 25. On-Chip Memory II (RAM or ROM) Intel FPGA IP 26. Optrex 16207 LCD Controller Core 27. PIO Core 28. PLL Cores 29. DMA Controller Core 30. Modular Scatter-Gather DMA Core 31. Scatter-Gather DMA Controller Core 32. SDRAM Controller Core 33. Tri-State SDRAM Core 34. Video Sync Generator and Pixel Converter Cores 35. Intel FPGA Interrupt Latency Counter Core 36. Performance Counter Unit Core 37. Vectored Interrupt Controller Core 38. Avalon® -ST Data Pattern Generator and Checker Cores 39. Avalon® -ST Test Pattern Generator and Checker Cores 40. System ID Peripheral Core 41. Avalon® Packets to Transactions Converter Core 42. Avalon® -ST Multiplexer and Demultiplexer Cores 43. Avalon® -ST Bytes to Packets and Packets to Bytes Converter IP 44. Avalon® -ST Delay Core 45. Avalon® -ST Round Robin Scheduler Core 46. Avalon® -ST Splitter Core 47. Avalon® -MM DDR Memory Half Rate Bridge Core 48. Intel FPGA GMII to RGMII Converter Core 49. HPS GMII to RGMII Adapter Intel® FPGA IP 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Altera ACE5-Lite Cache Coherency Translator 56. Lightweight UART Core

37.8.1.4. Funnel Latency

Funnel latency is the time required for the interrupt funnel to switch context. Funnel latency can include saving and restoring registers, managing preemption, and managing the stack pointer. Funnel latency depends on the following factors:

  • Whether a separate interrupt stack is used
  • The number of clock cycles required for load and store instructions
  • Whether the interrupt requires switching to a different register set
  • Whether the interrupt is preempting another interrupt within the same register set
  • Whether preemption within the register set is allowed

Preemption within the register set requires special attention. The HAL VIC driver provides special funnel code if an interrupt is allowed to preempt another interrupt assigned to the same register set. In this case, the funnel incurs additional overhead to save and restore the register contents. When creating the BSP, you can control preemption within the register set by using the VIC driver’s altera_vic_driver_enable_preemption_rs_<n> setting.

Note: With tightly-coupled memory, the Nios® II processor can execute a load or store instruction in 1 clock cycle. With onchip memory, not tightly-coupled, the processor requires two clock cycles.
Table 404.  Single Stack HAL latency
Funnel Type Clock Cycles Required for Load or Store
  1 2
Shadow register set, preemption within the register set disabled 10 13
Shadow register set, preemption within the register set enabled 42

Same register set (sstatus.SRS=0)

64

Same register set (sstatus.SRS=0)

26

Different register set (sstatus.SRS=1)

32

Different register set (sstatus.SRS=1)

Table 405.  Separate Interrupt Stack HAL Latency
Funnel Type Clock Cycles Required for Load or Store
  1 2
Shadow register set, preemption within the register set disabled 11

Not preempting another interrupt (sstatus.IH=0)

14

Not preempting another interrupt (sstatus.IH=0)

12

Preempting another interrupt (sstatus.IH=1)

15

Preempting another interrupt (sstatus.IH=1)

Shadow register set, preemption within the register set enabled 42

Same register set (sstatus.SRS=0)

64

Same register set (sstatus.SRS=0)

27
  • Different register set (sstatus.SRS=1)
  • Not preempting another interrupt (sstatus.IH=0)
33
  • Different register set (sstatus.SRS=1)
  • Not preempting another interrupt (sstatus.IH=0)
28
  • Different register set (sstatus.SRS=1)
  • Preempting another interrupt (sstatus.IH=1)
34
  • Different register set (sstatus.SRS=1)
  • Preempting another interrupt (sstatus.IH=1)

In the tables above, notice that the lowest latencies occur under the following conditions:

  • A different register set—Shadow register set switch; the ISR runs in a different register set from the interrupted task, eliminating any need to save or restore registers.
  • Preemption (nesting) within the register set disabled.

Conversely, the highest latencies occur under the following conditions:

  • The same register set—No shadow register set switch; the ISR runs in the same register set as the interrupted task, requiring the funnel code to save and restore registers.
  • Preemption within the register set enabled.

Of these two important factors, preemption makes the largest difference in latencies. With preemption disabled, much lower latencies occur regardless of other factors.