Avalon® Interface Specifications

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ID 683091
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
1. Introduction to the Avalon® Interface Specifications x
1.1. Avalon® Properties and Parameters 1.2. Signal Roles 1.3. Interface Timing 1.4. Example: Avalon® Interfaces in System Designs
2. Avalon® Clock and Reset Interfaces x
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
3. Avalon® Memory-Mapped Interfaces x
3.1. Introduction to Avalon® Memory-Mapped Interfaces 3.2. Avalon® Memory Mapped Interface Signal Roles 3.3. Interface Properties 3.4. Timing 3.5. Transfers 3.6. Address Alignment 3.7. Avalon® -MM Agent Addressing
3.5. Transfers x
3.5.1. Typical Read and Write Transfers 3.5.2. Transfers Using the waitrequestAllowance Property 3.5.3. Read and Write Transfers with Fixed Wait-States 3.5.4. Pipelined Transfers 3.5.5. Burst Transfers 3.5.6. Read and Write Responses
3.5.2. Transfers Using the waitrequestAllowance Property x
3.5.2.1. waitrequestAllowance Equals Two 3.5.2.2. waitrequestAllowance Equals One 3.5.2.3. waitrequestAllowance Equals Two - Not Recommended 3.5.2.4. waitrequestAllowance Compatibility for Avalon® -MM Host and Agent Interfaces 3.5.2.5. waitrequestAllowance Error Conditions
3.5.4. Pipelined Transfers x
3.5.4.1. Pipelined Read Transfer with Variable Latency 3.5.4.2. Pipelined Read Transfers with Fixed Latency
3.5.5. Burst Transfers x
3.5.5.1. Write Bursts 3.5.5.2. Read Bursts 3.5.5.3. Line–Wrapped Bursts
3.5.6. Read and Write Responses x
3.5.6.1. Transaction Order for Avalon® -MM Read and Write Responses (Hosts and Agents) 3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram
3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram x
3.5.6.2.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
4. Avalon® Interrupt Interfaces x
4.1. Interrupt Sender 4.2. Interrupt Receiver
4.1. Interrupt Sender x
4.1.1. Avalon® Interrupt Sender Signal Roles 4.1.2. Interrupt Sender Properties
4.2. Interrupt Receiver x
4.2.1. Avalon® Interrupt Receiver Signal Roles 4.2.2. Interrupt Receiver Properties 4.2.3. Interrupt Timing
5. Avalon® Streaming Interfaces x
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
5.3. Signal Sequencing and Timing x
5.3.1. Synchronous Interface 5.3.2. Clock Enables
5.9. Data Transfer with Backpressure x
5.9.1. Data Transfers Using readyLatency and readyAllowance 5.9.2. Data Transfers Using readyLatency
6. Avalon® Streaming Credit Interfaces x
6.1. Terms and Concepts 6.2. Avalon® Streaming Credit Interface Signal Roles 6.3. Avalon® Streaming Credit User Signals
6.2. Avalon® Streaming Credit Interface Signal Roles x
6.2.1. Synchronous Interface 6.2.2. Typical Data Transfers 6.2.3. Returning the Credits
6.3. Avalon® Streaming Credit User Signals x
6.3.1. Per-Symbol User Signal 6.3.2. Per-Packet User Signal
7. Avalon® Conduit Interfaces x
7.1. Avalon® Conduit Signal Roles 7.2. Conduit Properties
8. Avalon® Tristate Conduit Interface x
8.1. Avalon® Tristate Conduit Signal Roles 8.2. Tristate Conduit Properties 8.3. Tristate Conduit Timing
1. Introduction to the Avalon® Interface Specifications
2. Avalon® Clock and Reset Interfaces
3. Avalon® Memory-Mapped Interfaces
4. Avalon® Interrupt Interfaces
5. Avalon® Streaming Interfaces
6. Avalon® Streaming Credit Interfaces
7. Avalon® Conduit Interfaces
8. Avalon® Tristate Conduit Interface
A. Deprecated Signals
B. Document Revision History for the Avalon® Interface Specifications

3.5.4.1. Pipelined Read Transfer with Variable Latency

After capturing address and control signals, an Avalon® -MM pipelined agent takes one or more cycles to produce data. A pipelined agent may have multiple pending read transfers at any given time.

Variable-latency pipelined read transfers:
  • Require one additional signal, readdatavalid, that indicates when read data is valid.
  • Include the same set of signals as non-pipelined read transfers.
In variable-latency pipelined read transfers, Agent peripherals that use readdatavalid are considered pipelined with variable latency. The readdata and readdatavalid signals corresponding to a read command can be asserted the cycle after that read command is asserted, at the earliest.

The agent must return readdata in the same order that the read commands are accepted. Pipelined agent ports with variable latency must use waitrequest. The agent can assert waitrequest to stall transfers to maintain an acceptable number of pending transfers. An agent may assert readdatavalid to transfer data to the host independently of whether the agent is stalling a new command with waitrequest.

Note: The maximum number of pending transfers is a property of the agent interface. The interconnect fabric builds logic to route readdata to requesting hosts using this number. The agent interface, not the interconnect fabric, must track the number of pending reads. The agent must assert waitrequest to prevent the number of pending reads from exceeding the maximum number. If an agent has waitrequestAllowance > 0, the agent must assert waitrequest early enough so that the total pending transfers, including those accepted while waitrequest is asserted, does not exceed the maximum number of pending transfers specified.
Figure 12. Pipelined Read Transfers with Variable Latency

The following figure shows several agent read transfers. The agent is pipelined with variable latency. In this figure, the agent can accept a maximum of two pending transfers. The agent uses waitrequest to avoid overrunning this maximum.

The numbers in this timing diagram, mark the following transitions:

  1. The host asserts address and read, initiating a read transfer.
  2. The agent captures addr1.
  3. The agent captures addr2.
  4. The agent asserts waitrequest because the agent has already accepted a maximum of two pending reads, causing the third transfer to stall.
  5. The agent asserts data1, the response to addr1. The agent deasserts waitrequest.
  6. The agent captures addr3. The interconnect captures data1.
  7. The agent captures addr4. The interconnect captures data2.
  8. The agent drives readdatavalid and readdata in response to the third read transfer.
  9. The agent captures addr5. The interconnect captures data3. The read signal is deasserted. The value of waitrequest is no longer relevant.
  10. The interconnect captures data4.
  11. The agent drives data5 and asserts readdatavalid completing the data phase for the final pending read transfer.

If the agent cannot handle a write transfer while processing pending read transfers, the agent must assert waitrequest and stall the write operation until the pending read transfers have completed. The Avalon® -MM specification does not define the value of readdata in the event that an agent accepts a write transfer to the same address as a currently pending read transfer.

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