Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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2.1.10. Output Register Bank for Fixed-point Arithmetic

The positive edge of the clock signal triggers the 74-bit bypassable output register bank. The output register bank is not reset after power up and may hold unwanted data. Assert the CLR signal to clear the register before starting an operation.

The following variable precision DSP block signals control the output register per variable precision DSP block:

  • CLK
  • ENA[2..0]
  • CLR[1]