Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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5.5.1. Operation Mode Tab

Table 46.  Operation Mode Tab
Parameter IP Generated Parameter Value Default Value Description
Please choose the operation mode operation_mode

m9x9_sumof4

m18×18_full

m18×18_sumof2

m18×18_plus36

m18×18_systolic

m27×27

m18×18_full Select the desired operational mode.
1st Multiplier Configuration
Representation format for 'ax' operand signed_max

unsigned

signed

unsigned Specify the representation format for the first multiplier x operand.
Representation format for 'ay' operand signed_may

unsigned

signed

unsigned

Specify the representation format for the first multiplier y operand.

'ax' input bus width ax_width 0–27

Specify the width of ax input bus.

For more information about supported input width, refer to the related information.

Enable 'ax' input register ax_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for ax input register.

For more information about clock enable restrictions for input registers, refer to the related information.

'ay' or 'scanin' bus width ay_scan_in_width 1–27 18

Specify the width of ay or scanin input bus.

For more information about supported input width, refer to the related information.

Enable 'ay' or 'scanin' input register ay_scan_in_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for ay or scanin input register.

For more information about clock enable restrictions for input registers, refer to the related information.

2nd Multiplier Configuration
Representation format for 'bx' operand signed_mbx

unsigned

signed

unsigned Specify the representation format for second multiplier x operand.
Representation format for 'by' operand signed_mby

unsigned

signed

unsigned Specify the representation format for second multiplier y operand.

Always select unsigned for m18×18_plus36.

'bx' input bus width bx_width 0–36 18

Specify the width of bx input bus.

For more information about supported input width, refer to the related information.

Enable 'bx' input register bx_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for bx input register.

For more information about clock enable restrictions for input registers, refer to the related information.

'by' input bus width by_width 0–19 18

Specify the width of by input bus.

For more information about supported input width, refer to the related information.

Enable 'by' input register by_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for by input register.

For more information about clock enable restrictions for input registers, refer to the related information.

3rd Multiplier Configuration
Representation format for 'cx' operand signed_mcx

unsigned

signed

unsigned Specify the representation format for third multiplier x operand.

Only m9x9_sumof4 operational mode supports this parameter.

Representation format for 'cy' operand signed_mcy

unsigned

signed

unsigned Specify the representation format for third multiplier y operand.

Only m9x9_sumof4 operational mode supports this parameter.

'cx' input bus width cx_width 0–9 0 Specify the width of cx input bus.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about supported input width, refer to the related information.

Enable 'cx' input register cx_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for cx input register.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.

'cy' input bus width cy_width 0–9 0 Specify the width of cy input bus.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about supported input width, refer to the related information.

Enable 'cy' input register cy_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for cy input register.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.

4th Multiplier Configuration
Representation format for 'dx' operand signed_mdx

unsigned

signed

unsigned Specify the representation format for fourth multiplier x operand.

Only m9x9_sumof4 operational mode supports this parameter.

Representation format for 'dy' operand signed_mdy

unsigned

signed

unsigned Specify the representation format for fourth multiplier y operand.

Only m9x9_sumof4 operational mode supports this parameter.

'dx' input bus width dx_width 0–9 0 Specify the width of dx input bus.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about supported input width, refer to the related information.

Enable 'dx' input register dx_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for dx input register.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.

'dy' input bus width dy_width 0–9 0 Specify the width of dy input bus.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about supported input width, refer to the related information.

Enable 'dy' input register dy_clken

no_reg

ena0

ena1

ena2

no_reg Specify the clock enable signal for dy input register.

Only m9x9_sumof4 operational mode supports this parameter.

For more information about clock enable restrictions for input registers, refer to the related information.

Sub Configuration
Enable 'sub' port enable_sub

No

Yes

No

Select to enable sub port.

The sub port is an input signal that can be used dynamically to subtract the output of the top multiplier from the output of the bottom multiplier.

Only available for the following operation modes:
  • m18×18_full
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic

For more information about the sub port, refer to the related information.

Enable 'sub' input register sub_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for sub input register.
Only available for the following operation modes:
  • m18×18_full
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic

For more information about clock enable restrictions for input registers, refer to the related information.

Output 'result' Configuration
'resulta' output bus width result_a_width 1–64 37 Specify the width of resulta output bus.
'resultb' output bus width result_b_width 0–37 37 Specify the width of resultb output bus.

Only available for m18x18_full operation mode.

Enable output register output_clken

no_reg

ena0

ena1

ena2

ena0

Specify the clock enable signal for resulta and resultb output register.