Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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8.3.3. Pipelining Tab

Table 100.   Pipelining Tab
Parameter Value Default Value Description
Do you want to pipeline the function?
Pipeline

No

Yes

No Select Yes to enable pipeline register to the multiplier's output. Enabling the pipeline register adds extra latency to the output.
Latency Any value greater than 0. 1 Specify the desired output latency in clock cycle.
Clear Signal Type

NONE

ACLR

SCLR

NONE Specify the type of reset for the pipeline register.

Select NONE if you do not use any pipeline register.

Select ACLR to use asynchronous clear for the pipeline register. This generates ACLR port.

Select SCLR to use synchronous clear for the pipeline register. This generates SCLR port.

Create a 'clken' clock enable clock

Off

On

Off

Specifies active high clock enable for the clock port of the pipeline register
What type of optimization do you want?
Type

Default

Speed

Area

Default Specify the desired optimization for the IP core.

Select Default to let Intel® Quartus® Prime software to determine the best optimization for the IP core.