Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
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10.4.2. FP32 Addition or Subtraction Mode Signals

Figure 73. FP32 Addition or Subtraction Mode Signals
Table 113.   Data Input and Output Signals
Signal Name Type Width Default Description
fp32_adder_a[31:0] Input 32 Low Input data bus to the adder.
fp32_adder_b[31:0] Input 32 Low Input data bus to the adder.
fp32_result[31:0] Output 32 Output data bus from IP core.
fp32_chainout[31:0] Output 32 Connect these signals to the chainin signals of the next floating-point DSP IP core.
Table 114.  Clock, Enable, and Clear Signals
Signal Name Type Width Default Description
clk[0] Input 1 Input clock for all registers.
ena[2:0] Input 3 Clock enable signals for all registers.

These signals are active-High.

clr[1:0] Input 2 Low These signals can be asynchronous or synchronous clear input signals for all registers. You may select the type of clear input signal using Type of clear signal parameter.

These signals are active-High.

For more information about clock enable restrictions for input registers, refer to the related information.

Table 115.  Exception Flag Signals
Signal Name Type Width Default Description
fp32_adder_overflow Output 1

This signal indicates if the adder result is a larger value compared to the maximum representable value.

1: If the adder result is a larger value compared to the maximum presentable value and the result is cast to infinity.

0: If the adder result is not larger than the maximum presentable value.

fp32_adder_underflow Output 1

This signal indicates if the adder result is a smaller value compared to the minimum presentable value.

1: If the adder result is a smaller value compared to the minimum representable value and the result is flushed to zero.

0: If the adder result is a larger than the minimum representable value.

fp32_adder_inexact Output 1

This signal indicates if the adder result is an exact representation.

1: If the adder result is:
  • a rounded value
  • a smaller value compared to the minimum representable value or
  • a larger value compared to the maximum representable value.

0: If the adder result does not meet any of the criteria above.

fp32_adder_invalid Output 1

This signal indicates if the adder operation is ill-defined and produces an invalid result.

1: If the adder result is invalid and cast to qNaN.

0: If the adder result is not an invalid number.