Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
Public

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5.5.5. Accumulator/Output Chaining

Table 50.  Accumulator/Output Chaining Tab
Parameter IP Generated Parameter Value Default Value Description
Accumulator
Enable accumulate port enable_accumulate

No

Yes

No Select to enable accumulate port.
Only available for the following operational modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Enable 'accumulate' input register accumulate_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for accumulate input register.

Only available for the following operational modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27

For more information about clock enable restrictions for input registers, refer to the related information.

Enable double accumulator enable_double_accum

No

Yes

No Select to enable the double accumulator feature.
Only available for the following operational modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Negate
Enable 'negate' port enable_negate

No

Yes

No Select to enable negate port.
Only available for the following operational modes:
  • m18×18_sumof2
  • m18×18_systolic
  • m27×27
Enable 'negate' input register negate_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for negate input register.

Only available for the following operational modes:
  • m18×18_sumof2
  • m18×18_systolic
  • m27×27

For more information about clock enable restrictions for input registers, refer to the related information.

Loadconst
Enable 'loadconst' port enable_loadconst

No

Yes

No Select to enable loadconst port.
Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Enable 'loadconst' input register load_const_clken

no_reg

ena0

ena1

ena2

no_reg

Specify the clock enable signal for loadconst input register.

Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27

For more information about clock enable restrictions for input registers, refer to the related information.

N value of preset constant load_const_value 0–63 0 Specify the preset constant value.

This value can be 2N where N is the preset constant value.

Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Chainin/Chainout
Enable chainin port use_chainadder

No

Yes

No Select to enable chainin port.
Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Enable chainout port enable_chainout

No

Yes

No Select to enable chainout port.
Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Enable disable_chainout disable_chainout

No

Yes

No Select to enable disable_chainout port.
Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27
Set the chainin and chainout width chain_inout_width

0

44

64

0 Specify the width of chainin and chainout buses.
Only available for the following operation modes:
  • m9×9_sumof4
  • m18×18_sumof2
  • m18×18_plus36
  • m18×18_systolic
  • m27×27