Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.1.1. Input Register Bank for Fixed-point Arithmetic

The input register banks for fixed-point DSP blocks are available for the following input signals:
  • Data
  • Dynamic control signals
    • NEGATE
    • SUB
    • Dynamic Scanin
    • Dynamic Chainout

All the registers in the DSP blocks are positive-edge triggered. These registers are not reset after power up and may hold unwanted data. Assert the CLR signal to clear the registers before starting an operation.

Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.

The following variable precision DSP block signals control the input registers within the variable precision DSP block:
  • CLK
  • ENA[2..0]
  • CLR[0]
Figure 6. Data Input Registers in Fixed-point Arithmetic 9 x 9 Mode
Figure 7. Data Input Registers in Fixed-point Arithmetic 18 x 19 Mode
Figure 8. Data Input Registers in Fixed-point Arithmetic 27 x 27 Mode