Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 4/11/2023
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2. Intel® Agilex™ 7 Variable Precision DSP Blocks Architecture

The Intel® Agilex™ 7 variable precision DSP consists of the following blocks:
Table 5.  Block Architecture
DSP Implementations Block Architecture
Fixed-point Arithmetic
  • Input register bank
  • First and second pipeline registers
  • Pre-adder/subtract
  • Internal coefficient
  • Multipliers
  • Adder and Subtractor
  • Accumulator, chainout adder, and Preload Constant
  • Systolic registers
  • Double accumulation register
  • Output register bank
Floating-point Arithmetic
  • Input register bank
  • First and second pipeline registers
  • Multipliers
  • Adder
  • Accumulator
  • Output register bank
  • Exception Handling
Figure 1. Fixed-point Arithmetic 9 x 9 Mode
Figure 2. Fixed-point Arithmetic 18 x 19 Mode
Figure 3. Fixed-point Arithmetic 27 x 27 Mode
Figure 4. Floating-point Arithmetic 16-bit Half-Precision Mode
Figure 5. Floating-point Arithmetic 32-bit Single-Precision Mode