4.1.4. Input Cascade for Fixed-point Arithmetic
The input register bank in Intel® Agilex™ 7 variable precision DSP block supports input cascade feature. This feature provides the capability of cascading the input bus within a DSP block and to another DSP block.
- The top multiplier Y input drives the bottom multiplier Y input within a DSP block
- The bottom multiplier Y input of the first DSP block drives the top multiplier Y input of the subsequent DSP block
For 27 × 27 mode, the multiplier Y input of the first DSP block drives the multiplier Y input of the subsequent DSP block. This feature is not supported with pre-adder enabled.
There are two delay registers that you can use to balance the latency requirements when you use both the input cascade and chainout features in fixed-point arithmetic 18 x 19 mode. These are the top delay registers and bottom delay registers. The ay input register must be enabled when top delay register is enabled. The clock enable for both registers must be the same. Similarly, the by input register must be enabled when bottom delay register is enabled. The clock enable for both registers must be the same.
The delay registers are only supported in 18 x 18 or 18 x 19 independent multiplier, multiplier adder sum mode and 18-bit systolic FIR mode.